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| DM9102D Single Chip Fast Ethernet NIC Controller 1. General Description The DM9102D is a fully integrated and cost effective single chip Fast Ethernet NIC controller. It is designed with low power and high performance process. It is a 2.5/3.3V device with 5V tolerance. The DM9102D provides direct interface to the PCI bus and supports bus master mode to achieve the high performance of the PCI bus. It fully complies with PCI 2.2. In the media side, the DM9102D interfaces to the UTP3, 4, 5 in 10Base-T and the UTP5 in 100Base-TX. It is fully compliant with the IEEE 802.3u Spec. The auto-negotiation and HP Auto-MDIX function can automatically configure the DM9102D to take the maximum advantage of its abilities. The DM9102D also supports IEEE 802.3x's full-duplex flow control to prevent the receive overflow of link partner. The IPv4 IP/TCP/UDP checksum generation and checking can reduce the system CPU utilization. The DM9102D supports two types of power management mechanisms. The main mechanism is based on the OnNow architecture, which is required for PC99. The alternative mechanism is based upon the remote Wake-On-LAN mechanism. 2. Block Diagram Final Version: DM9102D-DS-F01 May 10, 2006 1 DM9102D Single Chip Fast Ethernet NIC Controller Table of Contents 1. General Description.............................................................1 2. Block Diagram......................................................................3 3. Features................................................................................4 4 Pin Configuration: DM9102D 128pin LQFP......................5 5. Pin Description...................................................................6 5.1 PCI Bus Interface Signals.................................................6 5.2 Boot ROM and EEPROM Interfaces..............................7 5.3 LED Pins.............................................................................8 5.4 Network Interface ..............................................................8 5.5 Miscellaneous Pins............................................................8 5.6 Power Pins.........................................................................9 5.7 NC Pins.............................................................................10 5.8 strap Pins..........................................................................10 6. Register Definition...........................................................11 6.1 PCI Configuration Registers...........................................11 6.1.1 Identification ID .............................................................12 6.1.2 Command & Status .....................................................13 6.1.3 Revision ID....................................................................14 6.1.4 Miscellaneous Function...............................................15 6.1.5 I/O Base Address.........................................................15 6.1.6 Memory Mapped Base Address................................16 6.1.7 Subsystem Identification..............................................16 6.1.8 Expansion ROM Base Address.................................17 6.1.9 Capabilities Pointer ......................................................17 6.1.10 Interrupt & Latency Configuration.............................18 6.1.11 Device Specific Configuration Register...................18 6.1.12 Power Management Register ..................................19 6.1.13 Power Management Control/Status ........................20 6.2 Control and Status Register (CR)..................................21 6.2.1 System Control Register (CR0)..................................22 6.2.2 Transmit Descriptor Poll Demand (CR1)...................22 6.2.3 Receive Descriptor Poll Demand (CR2) ...................22 6.2.4 Receive Descriptor Base Address (CR3)..................23 6.2.5 Transmit Descriptor Base Address (CR4).................23 6.2.6 Network Status Report Register (CR5).....................23 6.2.7 Network Operation Register (CR6)............................25 6.2.8 Interrupt Mask Register (CR7)....................................27 6.2.9 Statistical Counter Register (CR8) .............................28 6.2.10 Management Access Register (CR9) .....................29 6.2.11 PHY Status Register (CR12)....................................30 6.2.12 Sample Frame Access Register (CR13) ................30 2 6.2.13 Sample Frame Data Register (CR14).....................31 6.2.14 Watchdog and Jabber Timer Register (CR15) ......31 6.3 PHY Management Register Set....................................32 6.3.1 Basic Mode Control Register (BMCR) - Register 0 .............................................................................33 6.3.2 Basic Mode Status Register (BMSR) - Register 1 .............................................................................34 6.3.3 PHY Identifier Register #1 (PHYIDR1) - Register 2 .............................................................................35 6.3.4 PHY Identifier Register #2 (PHYIDR2) - Register 3 .............................................................................35 6.3.5 Auto-negotiation Advertisement Register (ANAR) - Register 4 .............................................................................35 6.3.6 Auto-negotiation Link Partner Ability Register (ANLPAR) - Register 5....................................................36 6.3.7 Auto-negotiation Expansion Register (ANER) - Register 6 .............................................................................37 6.3.8 DAVICOM Specified Configuration Register (DSCR) - Register 10H ........................................................................37 6.3.9 DAVICOM Specified Configuration and Status Register (DSCSR) - Register 11H.......................................38 6.3.10 10Base-T Configuration/Status (10BTSCRCSR) - Register 12H ........................................................................39 6.3.11 Power Down Control Register (PWDOR) - Register 13H ........................................................................40 6.3.12 HP Auto-MDIX ControlRegister (MDIX) - Register 14H ........................................................................40 7. Functional Description.......................................................41 7.1 System Buffer Management..........................................41 7.1.1 Overview .......................................................................41 7.1.2 Data Structure and Descriptor List.............................41 Figure 7-1....................................................41 7.1.3 Buffer Management: Chain Structure Method..........41 7.1.4 Descriptor List: Buffer Descriptor Format ..................41 7.2 Initialization Procedure....................................................46 7.2.1 Data Buffer Processing Algorithm..............................46 7.2.2 Receive Data Buffer Processing ................................46 Figure 7-2....................................................46 7.2.3 Transmit Data Buffer Processing ...............................47 Figure 7-3....................................................47 7.3 Network Function ............................................................48 7.3.1 Overview .......................................................................48 7.3.2 Receive Process and State Machine ........................48 7.3.3 Transmit Process and State Machine .......................48 Final Version: DM9102D-DS-F01 May 10, 2006 DM9102D Single Chip Fast Ethernet NIC Controller 7.3.4 Physical Layer Overview.............................................48 7.4 Serial Management Interface.........................................49 7.4.1 Management Interface - Read Frame Structure ....49 7.4.2 Management Interface - Write Frame Structure ...49 7.5 Power Management .......................................................51 7.5.1 Overview .......................................................................51 7.5.2 PCI Function Power Management Status ................51 7.5.3 The Power Management Operation..........................51 7.6 Sample Frame Programming Guide ............................53 7.7 EEPROM Overview........................................................54 7.7.1 Subsystem ID .............................................................54 7.7.2 Vendor ID ....................................................................54 7.7.3 Auto_ Load_ Control....................................................54 7.7.4 New_ Capabilities_ Enable.........................................54 7.7.5 PMC...............................................................................54 7.7.6 Byte Offset (15).............................................................54 7.7.7 Ethernet Address .........................................................55 7.7.8 Example of DM9102D EEPROM Format.................55 7.8 External MII Interface ......................................................56 7.8.1 The Sharing Pin Table.................................................56 8. DC and AC Electrical Characteristics..............................57 8.1 Absolute Maximum Ratings( 25C )..............................57 8.2 Operating Conditions ......................................................57 8.3 DC Electrical Characteristics..........................................58 8.4 AC Electrical Characteristics & Timing Waveforms ....59 8.4.1 PCI Clock Specifications Timing...........................59 8.4.2 Other PCI Signals Timing Diagram............................59 8.4.3 Boot ROM Timing ........................................................60 8.4.4 EEPROM Read Timing...............................................60 8.4.5 TP Interface...................................................................61 8.4.6 Oscillator/Crystal Timing..............................................61 8.4.7 Auto-negotiation and Fast Link Pulse Timing Parameters.....................................................................61 8.4.8 Fast Link Pulses...........................................................61 9. Application Notes...............................................................62 9.1 Network Interface Signal Routing..................................62 9.2 10Base-T/100Base-TX Application Figure 9-1 .........62 9.3 10Base-T/100Base-TX (Power Reduction Application) Figure 9-2.......................................................................63 9.4 Power Supply Decoupling Capacitors Figure 9-3.....64 9.5 Ground Plane Layout Figure 9-4-1 Figure 9-4-2 Figure 9-4-3 .............65 9.6 Power Plane Partitioning Figure 9-5...........................66 9.7 Magnetics Selection Guide Table 9-1: 10/100M Magnetic Sources......................67 Table 9-2: Magnetic Specification Requirements .....67 9.8 Crystal Selection Guide Table 9-3: Crystal Specifications.................................68 Figure 9-6: Crystal Circuit Diagram.............................68 10 Package Information........................................................69 Package Information (128 pin, LQFP) ...........................69 11. Ordering Information.........................................70 Final Version: DM9102D-DS-F01 May 10, 2006 3 DM9102D Single Chip Fast Ethernet NIC Controller 3. Features Integrated Fast Ethernet MAC, Physical Layer and transceiver in one chip. 128 pin LQFP with CMOS process. +2.5/3.3V Power supply with +5V tolerant I/O. Comply with PCI specification 2.2. PCI bus master architecture. PCI bus burst mode data transfer. Two large independent transmission and receipt FIFO. Up to 256K bytes Boot EPROM or Flash interface. EEPROM 93C46 interface automatically supports node ID load and configuration information. Comply with IEEE 802.3u 100Base-TX and 802.3 10Base-T. Comply with IEEE 802.3u auto-negotiation protocol for automatic link type selection. Support IEEE 802.3x Full Duplex Flow Control. VLAN frame length support. IP/TCP/UDP checksum generation and checking. Zero copy supporting. Comply with ACPI and PCI Bus Power Management. Support the MII (Media Independent Interface) for an external PHY. Support Wake-On-LAN function and remote wake-up (Magic packet, Link Change and Microsoft(R) wake-up frame). Support 4 Wake-On-LAN (WOL) signals (active high pulse, active low pulse, active high, active low.) High performance 100Mbps clock generator and data recovery circuit. Digital clock recovery circuit, using advanced digital algorithm to reduce jitter. Adaptive equalization circuit and Baseline wandering restoration circuit for 100Mbps receiver. Provides Loopback mode for easy system diagnostics. Support HP Auto-MDIX. Low power consumption modes: - Power reduced mode (cable detection) - Power down mode - Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction. (1.25:1 transformers for Non Auto-MDIX only). 4 Final Version: DM9102D-DS-F01 May 10, 2006 4. Pin Configuration : 128 pin LQFP BPCS#/EECS LINK&ACT# VCTRL25 SPD100# DVDD25 SPD10# IDSEL2 REQ2# GNT2# TEST2 DGND DGND EEDO DVDD AVDD EECK FDX# WOL NC MD7 MD6 MD5 MD4 85 84 75 93 91 89 88 83 74 82 80 87 86 79 78 77 76 73 72 92 81 71 70 95 94 90 69 68 96 X2 X1/OSC DGND AGND BGRESG BGRES AVDD25 AVDD25 RXI+ RXIAGND AGND TXO+ TXOAVDD25 AVDD25 INT# RST# PCICLK ISOLATE# GNT# REQ# PME# DVDD25 AD31 AD30 AD29 AD28 DGND AD27 AD26 AD25 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 12 13 14 28 10 11 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 31 32 1 2 3 4 5 6 7 8 9 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MD3 NC NC NC NC NC NC NC NC MD2 MD1 MD0/EEDI DVDD AD0/MA0 AD1/MA1 DGND AD2/MA2 AD3/MA3 AD4/MA4 AD5/MA5 DVDD DVDD AD6/MA6 AD7/MA7 AD8/MA8 CBE0# AD9/MA9 DGND DGND AD10/MA10 AD11/MA11 DVDD AD12/MA12 AD13/MA13 AD14/MA14 AD15/MA15 TEST1 CLOCKRUN# DGND CBE1# PAR DM9102D 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DEVSEL# IDSEL FRAME# CBE3# CBE2# DVDD AD23 DGND DVDD DVDD DVDD DVDD AD17/MA17 AD16/MA16 DVDD PERR# Final Version: DM9102D-DS-F01 May 10, 2006 SERR# IRDY# DGND DGND DGND DGND STOP# TRDY# DGND DVDD AD24 AD22 AD21 AD20 AD19 AD18 5 5. Pin Description I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power, # = asserted Low 5.1 PCI Bus Interface Signals Pin No. Pin Name I/O Description 128LQFP 113 INT# O/D Interrupt Request This signal will be asserted low when an interrupted condition as defined in CR5 is set, and the corresponding mask bit in CR7 is et. 114 RST# I System Reset When this signal is low, the DM9102D performs the internal system reset to its initial state. 115 PCICLK I PCI system clock PCI bus clock that provides timing for DM9102D related to PCI bus transactions. 117 GNT# I Bus Grant This signal is asserted low to indicate that DM9102D has been granted ownership of the bus by the central arbiter. 118 REQ# O Bus Request The DM9102D will assert this signal low to request the ownership of the bus. 119 PME# O/D Power Management Event. The DM9102D drives it low to indicates that a power management event has occurred. 3 IDSEL I Initialization Device Select This signal is asserted high during the Configuration Space read/write access. 21 FRAME# I/O Cycle Frame This signal is driven low by the DM9102D master mode to indicate the beginning and duration of a bus transaction. 23 IRDY# I/O Initiator Ready This signal is driven low when the master is ready to complete the current data phase of the transaction. A data phase is completed on any clock when both IRDY# and TRDY# are sampled asserted. 24 TRDY# I/O Target Ready This signal is driven low when the target is ready to complete the current data phase of the transaction. During a read, it indicates that valid data is asserted. During a write, it indicates that the target is prepared to accept data. 26 DEVSEL# I/O Device Select The DM9102D asserts the signal low when it recognizes its target address after FRAME# is asserted. As a bus master, the DM9102D will sample this signal which insures its destination address of the data transfer is recognized by a target. 27 STOP# I/O Stop This signal is asserted low by the target device to request the 6 Final Version: DM9102D-DS-F01 May 10, 2006 30 PERR# I/O 31 SERR# I/O 33 PAR I/O 2,20,34,48 C/BE3# C/BE2# C/BE1# C/BE0# I/O 121,122,123,124,126,127, 128,1,6,7,10,11,13,14,16, 17,38,39,40,41,43,44,47, 49,50,51,54,55,56,57,59, 60 AD31~AD0/ MA17~MA0 I/O master device to stop the current transaction. Parity Error The DM9102D as a master or slave will assert this signal low to indicate a parity error on any incoming data. System Error This signal is asserted low when address parity is detected with enabled PCICS bit31 (detected parity error.) The system error asserts two clock cycles after the falling address if an address parity error is detected. Parity This signal indicates even parity across AD0~AD31 and C/BE0#~C/BE3# including the PAR pin. This signal is an output for the master and an input for the slave device. It is stable and valid one clock after the address phase. Bus Command/Byte Enable During the address phase, these signals define the bus command or the type of bus transaction that will take place. During the data phase these pins indicate which byte lanes contain valid data. C/BE0# applies to bit7-0 and C/BE3# applies to bit31-24. Address & Data or Boot ROM Address These are multiplexed address and data bus signals. As a bus master, the DM9102D will drive address during the first bus phase. During subsequent phases, the DM9102D will either read or write data expecting the target to increment its address pointer. As a target, the DM9102D will decode each address on the bus and respond if it is the target being addressed. AD17~AD0 can also be used as boot ROM address MA17~MA0 when the boot ROM is accessed. 5.2 Boot ROM and EEPROM Interfaces Pin Name Pin No. 128LQFP 62 MD0/EEDI I/O I Description Boot ROM Data Input/EEPROM Data In This is a multiplexed pin used by EEDI and MD0. When boot ROM is selected, it acts as boot ROM data input, otherwise the DM9102D will read the contents of EEPROM serially through this pin. Boot ROM Data Input Bus Boot ROM (active low )or EEPROM Chip Selection. EEPROM Data Out This pin is used serially to write op-codes, addresses and data into the EEPROM. EEPROM Serial Clock This pin is used as the clock for the EEPROM data transfer. 63,64,65,66,67,68,69 72 78 MD1~MD7 BPCS#/EECS EEDO I O O 79 EECK O 5.3 LED Pins Pin No. 128LQFP 87 Final Version: DM9102D-DS-F01 May 10, 2006 Pin Name LINK&ACT# I/O O/D Description LED Output Pin, Active Low 7 88 FDX# O/D 89 SPD100# O/D 90 SPD10# O/D mode 0 = Link and traffic LED. Active low to indicate normal link, and it will flash as a traffic LED when transmitting or receiving. mode 1 = traffic LED only LED Output Pin, Active Low mode 0 = Full duplex LED mode 1 = Full duplex LED LED Output Pin, Active Low mode 0 = 100Mbps LED mode 1 = 100Mbps LED LED Output Pin, Active Low mode 0 = 10Mbps LED mode 1 = Link LED 5.4 Network Interface Pin No. 128LQFP 105,106 Pin Name RXI+ RX- I/O I Description 100M/10Mbps Differential Input Pair. These two pins are differential receive input pair for 100BASE-TX and 10BASE-T. They are capable of receiving 100BASE-TX MLT-3 or 10BASE-T Manchester encoded data. 100M/10Mbps differential output pair. These two pins are differential output pair for 100BASE-TX and 10BASE-T. This output pair provides controlled rising and falling time, designed to filter the transmitter's output. 109,110 TXO+ TXO- O 5.5 Miscellaneous Pins Pin No. 128LQFP 75 Pin Name IDSEL2 I/O O Description PCI IDSEL 2. When this pin is pulled high, the PCI multiple function is present, and it act as PCI IDSEL2 function. PCI Request 2 If the PCI multiple function mode is selected, this pin act as the PCI REQ2# function. PCI GNT2# If the PCI multiple function mode is selected, this pin act as GNT2# function. When this pin is pulled high, the DM9102D is in LED mode 1 otherwise the led mode 0 is selected. Clockrun# The clockrun# signal is used by the system to pause or slow down the PCI clock signal. It is used by the DM9102D to enable or disable suspension or restart of the PCI clock. When the CLOCKRUN# pin is not used, this pin should be connected to an external pulled down resistor. TEST mode control 2 In normal operation, tie high to this pin. Final Version: DM9102D-DS-F01 May 10, 2006 84 REQ2# O 83 GNT2# I 36 CLOCKRUN# I/O 71 TEST2 I 8 37 94 TEST1 WOL I O 97 X2 O 98 X1/OSC I 102 BGRES I 116 ISOLATE# I TEST Mode Control 1 In normal operation, tie low to this pin. Wake up signal. The DM9102D can assert this pin if it detects link status change, magic packet, or sample frame match. The default is low active pulse mode. The DM9102D also supports High/Low and Pulse/Level options from EEPROM setting. Crystal feedback output This pin is used for crystal connection only. Leave this pin open if oscillator is used. Crystal or Oscillator Input. (25MHz 50ppm) Connect to a 25MHz Oscillator or series resonance, fundamental frequency crystal. Bandgap Voltage Reference Resistor. It connects to a 6.8K 1% error tolerance resistor between this pin and BGRESG pin, to provide an accurate current reference for DM9102D (10Base-T/100Base-TX Application). Isolate This pin is used to isolate the DM9102D from the PCI bus. 95 VCTRL25 O Voltage 2.5V control This pin can be used to control a BJT transistor `s base pin to generate a stable 2.5V power in BJT's drain pin . 5.6 Power Pins Pin No. 128LQFP 101 100,107,108 103,104,111,112 96 8,9,15,22,28,29,35,45, 46,58,76,86,99,125 82,120 4,5,12,18,19,25,32,42,52, 53,61,70 Pin Name BGRESG AGND AVDD25 AVDD DGND DVDD25 DVDD I/O P P P P P P P Description Bandgap Ground It is used together with the BGRES pin. Analog Ground Analog Power, +2.5V Analog Power, +3.3V Digital Ground Digital Power, +2.5V Digital Power, +3.3V Final Version: DM9102D-DS-F01 May 10, 2006 9 5.7 NC Pins Pin No. 128LQFP 73,74,77,80,81,85,91,92, 93 5.8 strap pins table Pin Name NC I/O - Description These pins are unused in application and should let them unconnected. 1: pull-high 1K~10K, 0: default floating. Pin No. Pin Name Description 72 BPCS#/EECS Disable HP Auto-MDIX 1: HP Auto-MDIX disabled 0: HP Auto-MDIX enabled PCI multiple function 1: enable PCI multiple function 0: disable PCI multiple function LED mode 75 IDSEL2 83 GNT2# 1: LED mode 1 0: LED mode 0 10 Final Version: DM9102D-DS-F01 May 10, 2006 6. Register Definition 6.1 PCI Configuration Registers The definitions of PCI Configuration Registers are based on the PCI specification revision 2.2 and it provides the initialization and configuration information to operate the PCI interface in the DM9102D. All registers can be accessed with byte, word, or double word mode. As defined in PCI specification 2.1, read accesses to reserve or unimplemented registers will return a value of "0." These registers are to be described in the following sections. The default value of PCI configuration registers after reset. Description Identifier Address Offset Value of Reset Identification PCIID 00H 91021282H Command & Status PCICS 04H 02100000H* Revision PCIRV 08H 02000051H Miscellaneous PCILT 0CH BIOS determine I/O Base Address PCIIO 10H System allocate Memory Base Address PCIMEM 14H System allocate Reserved -------18H - 28H 00000000H Subsystem Identification PCISID 2CH load from EEPROM Expansion ROM Base Address PCIROM 30H 00000000H Capability Pointer CAP_PTR 34H 00000050H Reserved -------38H 00000000H Interrupt & Latency PCIINT 3CH System allocate bit7~0 Device Specific Configuration Register PCIUSR 40H 00000000H** Power Management Register PCIPMR 50H C0310001H** Power Management Control & Status PMCSR 54H 00000100H * It is written to 02100007H by most BIOS. ** It may be changed from EEPROM in application. Key to Default In the register description that follows, the default column takes the form Final Version: DM9102D-DS-F01 May 10, 2006 11 6.1.1 Identification ID (xxxxxx00H - PCIID) 31 16 15 0 Dev_ID Device ID Vendor ID Vend_ID Bit 16:31 0:15 Default 9102H 1282H Type RO RO Description The field identifies the particular device. Unique and fixed number for the DM9102D is 9102H. This field identifies the manufacturer of the device. Unique and fixed number for Davicom is 1282H. 6.1.2 Command & Status (xxxxxx04H - PCICS) 31 16 15 0 Status Status Command Command 31 30 29 28 27 26 25 24 23 22 21 20 19 0 Detected Parity Error Signal For System Error 10 9 Reserved 0 8 7 0 6 5 0 4 0 3 2 1 0 01 0 0 0 1 Master Abort Detected Target Abort Detected Send Target Abort DEVSEL Timing Data Parity Error Detected Slave mode Fast back to Back User Definable 66MHz Capability New Capability Mast Mode Fast Back-To-Back SERR# Driver Enable/Disable Address/Data Steeping Parity Error Response Enable/Disable VGA Palette snoop Memory Write and Invalid Special Cycle Master Device Capability Enable/Disable Memory Space Access Enable/Disable I/O Space Access Enable/Disable 12 Final Version: DM9102D-DS-F01 May 10, 2006 Bit 31 Default 0 Type R/C Description Detected Parity Error The DM9102D samples the AD[0:31], C/BE[0:3]#, and the PAR signal to check parity and to set parity errors. In slave mode, the parity check falls on command phase and data valid phase (IRDY# and TRDY# both active). In master mode, the DM9102D will check each data phase, during a memory read cycle, for parity error. During a memory write cycle, if an error occurs, the PERR# signal will be driven by the target. This bit is set by the DM9102D and cleared by writing "1". There is no effect by writing "0" Signal For System Error This bit is set when the SERR# signal is driven by the DM9102D. This system error occurs when an address parity is detected under the condition that bit 8 and bit 6 in command register below are set Master Abort Detected This bit is set when the DM9102D terminates a master cycle with the master-abort bus transaction Target Abort Detected This bit is set when the DM9102D terminates a master cycle due to a target-abort signal from other targets Send Target Abort (0 for No Implementation) The DM9102D will never assert the target-abort sequence DEVSEL Timing (01 Select Medium Timing) Medium timing of DEVSEL# means the DM9102D will assert DEVSEL# signal two clocks after FRAME# is sample "asserted" Data Parity Error Detected This bit will take effect only when operating as a master and when a Parity Error Response Bit in command configuration register is set. It is set under two conditions: (i) PERR# asserted by the DM9102D in memory data read error (ii) PERR# sent from the target due to memory data write error Slave Mode Fast Back-To-Back Capable (0 for No Support) This bit is always reads "1" to indicate that the DM9102D is capable of accepting fast back-to-back transaction as a slave mode device User-Definable Feature Supported (0 for No Support) 66 MHz (0 for No Capability) New Capability This bit indicates whether this function implements a list of extended capabilities such as PCI power management. This bit may be updated by EEPROM. When set this bit indicates the presence of New Capability. A value of 0 means that this function does not implement New Capability Reserved Master Mode Fast Back-To-Back (0 for No Support) The DM9102D does not support master mode fast back-to-back capability and will not generate fast back-to-back cycles SERR# Driver Enable/Disable This bit controls the assertion of SERR# signal output. The SERR# output will be asserted on detection of an address parity error and if both this bit and bit 6 are set Address/Data Stepping (0 for No Stepping) Parity Error Response Enable/Disable 13 30 0 R/C 29 0 R/C 28 0 R/C 27 26:25 0 01 R/C R/C 24 0 R/C 23 0 RO 22 21 20 0 0 1 RO RO RO 19:10 9 0 0 RO RO 8 0 RW 7 6 Final 0 0 RO RW Version: DM9102D-DS-F01 May 10, 2006 5 4 3 2 1 0 0 0 1 1 RO RO RO RW RW 0 1 RW Setting this bit will enable the DM9102D to assert PERR# on the detection of a data parity error and to assert SERR# for reporting address parity error VGA Palette Snooping (0 for No Support) Memory Write and Invalid (0 for No Implementation) The DM9102D only generates memory write cycle Special Cycles (0 for No Implementation) Master Device Capability Enable/Disable When this bit is set, DM9102D has the ability of master mode operation Memory Space Access Enable/Disable This bit controls the ability of memory space access. The memory access includes memory mapped I/O access and Boot ROM access. As the system boots up, this bit will be enabled by BIOS for Boot ROM memory access. While in normal operation, using memory mapped I/O access, this bit should be set by driver before memory access cycles I/O Space Access Enable/Disable This bit controls the ability of I/O space access. It will be set by BIOS after power on 6.1.3 Revision ID (xxxxxx08H - PCIRV) 31 Class Code Class Code Revision Major Number Revision Minor Number 8 7 4 3 0 Revision ID Bit 31:8 7:4 Default 020000H 0101 Type RO RO 3:0 0001 RO Description Class Code (020000H) This is the standard code for Ethernet LAN controller Revision Major Number This is the silicon-major revision number that will increase for the subsequent versions of the DM9102D Revision Minor Number This is the silicon-minor revision number that will increase for the subsequent versions of the DM9102D 14 Final Version: DM9102D-DS-F01 May 10, 2006 6.1.4 Miscellaneous Function (xxxxxx0cH - PCILT) 31 BIST 24 23 Header Type 16 15 Latency Timer 8 7 Cache Line Size 0 Built-In Self Test Header Type Latency Timer For The Bus Master Cache Line Size For Memory Read Bit 31:24 23:16 15:8 Default 00H 00H 00H Type RO RO RW 7:0 00H RO Description Built In Self Test ( 00H means No Implementation) Header Type ( 00H means single function with Predefined Header Type ) If pin 75 IDSEL2 is pull-high, header type is 80H means multiple function is present. Latency Timer For The Bus Master The latency timer is guaranteed by the system and measured by clock cycles. When the FRAME# is asserted at the beginning of a master period by the DM9102D, the value will be copied into a counter and start counting down. If the FRAME# is de-asserted prior to count expiration, this value is meaningless. When the count expires before GNT# is de-asserted, the master transaction will be terminated as soon as the GNT# is removed While GNT# signal is removed and the counter is non-zero, the DM9102D will continue with its data transfers until the count expires. The system host will read MIN_GNT and MAX_LAT registers to determine the latency requirement for the device and then initialize the latency timer with an appropriate value The reset value of Latency Timer is determined by BIOS Cache Line Size For Memory Read Mode Selection ( 00H means No Implementation For Use) 6.1.5 I/O Base Address (xxxxxx10H - PCIIO) 31 I/O Base Address I/O Base Address PCI I/O Range Indication I/O or Memory Space Indicator 87 0000000 1 1 0 Final Version: DM9102D-DS-F01 May 10, 2006 15 Bit 31:7 Default Undefined Type RW 6:1 0 000000 1 RO RO Description PCI I/O Base Address This is the base address value for I/O accesses cycles. It will be compared to AD[31:7] in the address phase of bus command cycle for the I/O resource access PCI I/O Range Indication It indicates that the minimum I/O resource size is 80h I/O Space Or Memory Space Base Indicator Determines that the register maps into the I/O space ( = 1 Indicates I/O Base) 6.1.6 Memory Mapped Base Address (xxxxxx14H - PCIMEM) 31 Memory Base Address Memory Base Address Memory Range Indication I/O Or Memory Space Indicator 8 7 0000000 1 0 0 Bit 31:7 Default Undefined Type R/W 6:1 0 000000 0 RO RO Description PCI Memory Base Address This is the base address value for memory accesses cycles. It will be compared to the AD [31:7] in the address phase of bus command cycle for the Memory resource access PCI Memory Range Indication It indicates that the minimum memory resource size is 80h I/O Space Or Memory Space Base Indicator Determines that the register maps into the memory space( = 0 Indicates Memory Base) 6.1.7 Subsystem Identification (xxxxxx2cH - PCISID) 31 Subsystem ID Subsystem ID Subsystem Vendor ID Subsystem Vendor ID 0 Bit 31:16 15:0 Default XXXXH XXXXH Type RO RO Description Subsystem ID It can be loaded from EEPROM word 1 Subsystem Vendor ID It can be loaded from EEPROM word 0 16 Final Version: DM9102D-DS-F01 May 10, 2006 6.1.8 Expansion ROM Base Address (xxxxxx30 - PCIROM) 31 ROM Base Address ROM Base Address 18 17 00000000 0000000 10 9 Reserved 1 0 R/W Bit 31:10 9:1 0 Default 00H 000000000 0 Type RW RO RW Description ROM Base Address With 256K Boundary PCIROM bit17~10 are hardwired to 0, indicating ROM Size is up to 256K Size Reserved Bits Read As 0 Expansion ROM Decoder Enable/Disable If this bit and the memory space access bit are both set to 1, the DM9102D will respond to its expansion ROM 6.1.9 Capabilities Pointer (xxxxxx34H - Cap _Ptr) 31 Reserved 8 7 01 01 000 0 0 Capability Pointer Bit 31:8 7:0 Default 000000H 01010000 Type RO RO Description Reserved Capability Pointer The Cap_ Ptr provides an offset (default is 50H) into the function's PCI Configuration Space for the location of the first term in the Capabilities Linked List. The Cap_ Ptr offset is double word aligned so the two least significant bits are always "0"s Final Version: DM9102D-DS-F01 May 10, 2006 17 6.1.10 Interrupt & Latency Configuration (xxxxxx3cH - PCIINT) 31 MAX_LAT Maximum Latency Timer Minimum Grant Interrupt Pin Interrupt Line 24 23 MIN_GNT 16 15 INT_PIN 8 7 INT_LINE 0 Bit 31:24 23:16 15:8 7:0 Default 28H 14H 01H XXH Type RO RO RO RW Description Maximum Latency Timer that can be sustained. Minimum Grant Minimum Length of a Burst Period. Interrupt Pin read as 01H to indicate INTA# Interrupt Line that Is routed to the Interrupt Controller The value depends on system software. 6.1.11 Device Specific Configuration Register (xxxxxx40H- PCIUSR) 31 30 29 28 27 26 25 24 23 Reserved Device Specific Link Event enable/disable Sample Frame Event enable/disable Magic Packet Event enable/disable Link Event Status Sample Frame Event Status Magic Packet Event Status Device Specific 16 15 87 Reserved 0 Bit 31 30 29 28 27 26 25 24 23:16 15:8 7:0 Default 0 0 0 0 0 0 0 0 00H 00H 00H Type RW RW RW RW RW RO RO RO RO RW RO Description Device Specific Bit (sleep mode) Device Specific Bit (snooze mode) When set, enables Link Status Change Wake up Event When set, enables Sample Frame Wake up Event When set, enables Magic Packet Wake up Event When set, indicates the Link Change and the Link Status Change Event occurred When set, indicates the Sample Frame is received and the Sample Frame match Event occurred When set, indicates the Magic Packet is received and the Magic packet Event occurred Reserved Bits Read As 0 Device Specific Reserved Bits Read As 0 18 Final Version: DM9102D-DS-F01 May 10, 2006 6.1.12 Power Management Register (xxxxxx50H~PCIPMR) 31 PMC Power Management Capabilities Next Item Pointer Capability Identifier 16 15 Next Item Pointer 87 Capability ID 0 Bit 31:27 Default 11000 Type RO 26:25 24:22 00 011 RO RO 21 1 RO 20 19 18:16 0 0 010 RO RO RO 15:8 00H RO 7:0 01H RO Description PME_ Support This field indicates that the power states in which the function may assert PME#. A value of 0 for any bit indicates that the function is not capable of asserting the PME# signal while in that power state bit27 PME# support D0 bit28 PME# support D1 bit29 PME# support D2 bit30 PME# support D3(hot) bit31 PME# support D3(cold) DM9102D's bit31~27=11000 indicates PME# can be asserted from D3(hot) & D3(cold) These bits can be load from EEPROM word 7 bit [7:3] Reserved These two bits can be load from EEPROM word 7 bit [1:0] Aux_ Current This field reports the 3.3Vaux auxiliary current requirement for the PCI function. The default value of this field is 011 means 160mA and it can be loaded from EEPROM word 4 bit [15:13] if EEPROM word 4 bit [9] is 1 A "1" indicates that the function requires a device specific initialization sequence following transition to the D0 uninitialized state This bit can be load from EEPROM word 7 bit [2] Reserved PME# Clock "0" indicates that no PCI clock is required for the function to generate PME# Version A default value of 010 indicates that this function complies with the Revision 1.1 of the PCI Power Management Interface Specification This value can be loaded from EEPROM word 4 bit [12:10] if EEPROM word 4 bit [9] is 1 Next Item Pointer The offset into the function's PCI Configuration Space pointing to the location of next item in the function's capability list is "00H" Capability Identifier When "01H" indicates the linked list item as being the PCI Power Management Registers Final Version: DM9102D-DS-F01 May 10, 2006 19 6.1.13 Power Management Control/Status (xxxxxx54H~PMCSR) 31 Reserved 16 15 R/W 14 Reserved 9 8 R/W 7 Reserved 2 10 R/W PME_Status PME_En Power_State Bit 31:16 15 Default 0000H 0 Type RO RW/C Description Reserved PME_ Status This bit is set when the function would normally assert the PME# signal independent of the state of the PME_ En bit. Writing a "1" to this bit will clear it. This bit defaults to "0" if the function does not support PME# generation from D3 (cold).If the function supports PME# from D3 (cold) then this bit is sticky and must be explicitly cleared by the operating system whenever the operating system is initially loaded. Reserved It means that the DM9102D does not support reporting power consumption. PME_ En Write "1" to enables the function to assert PME#, write "0" to disable PME# assertion This bit defaults to "0" if the function does not support PME# generation from D3 (cold) If the function supports PME# from D3(cold) then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. Reserved This two bits field is both used to determine the current power state of a function and to set the function into a new power state. The definitions given below 00: D0 11: D3 (hot) 14:9 8 000000 1 RO RW 7:2 1:0 000000 00 RO RW 20 Final Version: DM9102D-DS-F01 May 10, 2006 6.2 Control and Status Registers (CR) The DM9102D implements 16 control and status registers, which can be accessed by the host. These CRs are double long word aligned. All CRs are set to their default values by hardware or software reset unless otherwise specified. All Control and Status Registers with their definitions and offset from IO or memory Base Address are shown below: Register CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 Description System Control Register Transmit Descriptor Poll Demand Receive Descriptor Poll Demand Receive Descriptor Base Address Register Transmit Descriptor Base Address Register Network Status Report Register Network Operation Mode Register Interrupt Mask Register Statistical Counter Register External Management Access Register Reserved Reserved PHY Status Register Sample Frame Access Register Sample Frame Data Register Watchdog And Jabber Timer Register Offset from CSR Base Address 00H 08H 10H 18H 20H 28H 30H 38H 40H 48H 50H 58H 60H 68H 70H 78H Default value after reset DE000000H FFFFFFFFH FFFFFFFFH 00000000H 00000000H FC000000H 02040000H FFFE0000H 00000000H 000083F0H FFFFFFFFH FFFE0000H FFFFFFXXH XXXXXX00H Unpredictable 00000000H Key to Default In the register description that follows, the default column takes the form: Final Version: DM9102D-DS-F01 May 10, 2006 21 6.2.1 System Control Register (CR0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 31:24 25:22 21 Name Reserved Reserved MRM Default DEH,RO 00,RO 0,RW 20:1 0 Reserved SR 0,RO 0,RW Description Reserved Reserved Memory Read Multiple When set, the DM9102D will use memory read multiple command (C/BE3~0 1100) when it initialize the memory read burst transaction as a master device When reset, it will use memory read command (C/BE3 ~ 0 = 0110) for the same master operation Reserved Software Reset When set, the DM9102D will make a internal reset cycle. All consequent action to DM9102D2 should wait at least 32 PCI clock cycles for its self-cleared. 6.2.2 Transmit Descriptor Poll Demand (CR1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 31:0 Name TDP Default FFFFFFFFH ,WO Description Transmit Descriptor Polling Command Writing any value to this port will force DM9102D to poll the transmit descriptor. If the acting descriptor is not available, transmit process will return to suspend state. If the descriptor shows buffer available, transmit process will begin the data transfer. 6.2.3 Receive Descriptor Poll Demand (CR2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 31:0 Name RDP Default FFFFFFFFH ,WO Description Receive Descriptor Polling Command Writing any value to this port will force DM9102D to poll the receive descriptor. If the acting descriptor is not available, receive process will return to suspend state. If the descriptor shows buffer available, receive process will begin the data transfer. 6.2.4 Receive Descriptor Base Address (CR3) 22 Final Version: DM9102D-DS-F01 May 10, 2006 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 00 Bit 31:0 Name RDBA Default 00000000H, RW Description Receive Descriptor Base Address This register defines base address of receive descriptor-chain. The receive descriptor- polling command, after CR3 is set, will make DM9102D to fetch the descriptor at the Base-Address. This is a working register, so the value of reading is unpredictable. 6.2.5 Transmit Descriptor Base Address (CR4) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 00 Bit 31:0 Name TDBA Default 00000000H, RW Description Transmit Descriptor Base Address This register defines base address of transmit descriptor-chain. The transmit descriptor- polling command after CR4 is set to make DM9102D fetch the descriptor at the Base-Address. This is a working register, so the value of reading is unpredictable. 6.2.6 Network Status Report Register (CR5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: Bits [13:0] can be cleared by written 1 to them respectively. Bit Name Default Description 31:26 Reserved 000000,RO Reserved 25:23 SBEB 000,RO System Bus Error Bits These bits are read only and used to indicate the type of system bus fatal error. Valid only when System Bus Error is set. The mapping bits are shown below Bit25 Bit24 Bit23 Bus Error Type 0 0 0 Parity error 0 0 1 Master abort 0 1 0 Slave abort 0 1 1 Reserved 1 X X Reserved Transmit Process State These bits are read only and used to indicate the state of transmit process The mapping table is shown below Bit22 Bit21 Bit20 Process State 0 0 0 Transmit process stopped 0 0 1 Fetch transmit descriptor 0 1 0 Move Setup Frame from the host memory 23 22:20 TXPS 000,RO Final Version: DM9102D-DS-F01 May 10, 2006 19:17 RXPS 000,RO 16 NIS 0,RW 15 AIS 0,RW 14 13 Reserved SBE 0,RO 0,RW 12 11:10 9 8 7 LINK Reserved RXWT RXPS RXDU 0,RW 0,RO 0,RW 0,RW 0,RW 6 RXCI 0,RW 5 TXFU 0,RW 4 24 Reserved 0,RO 0 1 1 Move data from host memory to transmit FIFO 1 0 0 Close descriptor by clearing owner bit of descriptor 1 0 1 Waiting end of transmit 1 1 0 Transmit end and Close descriptor by writing status 1 1 1 Transmit process suspend Receive Process State These bits are read only and used to indicate the state of receive process. The mapping table is shown below Bit19 Bit18 Bit17 Process State 0 0 0 Receive process stopped 0 0 1 Fetch receive descriptor 0 1 0 Wait for receive packet under buffer available 0 1 1 Move data from receive FIFO to host memory 1 0 0 Close descriptor by clearing owner bit of descriptor 1 0 1 Close descriptor by writing status 1 1 0 Receive process suspended due to buffer unavailable 1 1 1 Purge the current frame from received FIFO because of the unavailable received buffer Normal Interrupt Summary Normal interrupt includes any of the three conditions: CR5<0> - TXCI: Transmit Complete Interrupt CR5<2> - TXDU: Transmit Buffer Unavailable CR5<6> - RXCI: Receive Complete Interrupt Abnormal Interrupt Summary Abnormal interrupt includes any interrupt condition as shown below, excluding Normal Interrupt conditions. They are TXPS (bit1), TXJT (bit3), TXFU (bit5), RXDU (bit7), RXPS (bit8), RXWT (bit9), SBE (bit13). Reserved System Bus Error The PCI system bus errors will set this bit. The type of system bus error is shown in CR5<25:23>. Link Change Status This bit is set to indicate that the link status changed in internal PHYceiver. Reserved Receive Watchdog Timer Expired This bit is set to indicate that the receive watchdog timer has expired Receive Process Stopped This bit is set to indicate that the receive process enters the stopped state. Receive Buffer Unavailable This bit is set when the DM9102D fetches the next receive descriptor that is still owned by the host. Receive process will be suspended until a new frame enters or the receive polling command is set. Receive Complete Interrupt This bit is set when a received frame is fully moved into host memory and receive status has been written to descriptor. Receive process is still running and continues to fetch next descriptor. Transmit FIFO Underrun This bit is set when transmit FIFO has underrun condition during the packet transmission. It may happen due to the heavy load on bus, cause transmit buffer unavailable before end of packet. In this case, transmit process is placed in the suspend state and underrun error TDES0<1> is set. Reserved Final Version: DM9102D-DS-F01 May 10, 2006 3 TXJT 0,RW 2 TXDU 0,RW 1 0 TXPS TXCI 0,RW 0,RW Transmit Jabber Expired This bit is set when the transmitted data is over 2048 byte Transmit process will be aborted and placed in the stop state. It also causes transmit jabber timeout TDES0<14> to assert. Transmit Buffer Unavailable This bit is set when the DM9102D fetches the next transmit descriptor that is still owned by the host. Transmit process will be suspended until the transmission polling command is set. Transmit Process Stopped This bit is set to indicate transmit process enters the stopped state. Transmit Complete Interrupt This bit is set when a frame is fully transmitted and transmit status has been written to descriptor (the TDES1<31> is also asserted). Transmit process is still running and continues to fetch next descriptor. 6.2.7 Network Operation Mode Register (CR6) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 0 0 0 0 Bit 31 30 Name Reserved RXA Default 0,RO 0,RW 29 28:26 25 24:23 22 NPFIFO Reserved Reserved Reserved TXTM 0,RW 000,RO 1,RO 00,RO 1,RW 21 SFT 0,RW 20 19 18 17 16 Reserved Reserved External MII_ Mode Reserved 1PKT 0,RW 0,RW 1,RW 0,RO 0,RW Description Must be Zero Receive All When set, all incoming packet will be received, regardless the destination address. The address match is checked according to theCR6<7>, CR6<6>, CR6<4>, CR6<2>, CR6<0>, and RDES0<30> will show this match Set to not purge RX FIFO for test only if RX buffer unavailable. Must be Zero Must be One Must be Zero Transmit Threshold Mode When set, the transmit threshold mode is 10Mb/s. When reset, the threshold mode is 100Mb/s. This bit is used together with CR6<15:14> to decide the exact threshold level. Store and Forward Transmit When set, the packet transmission will be started after a full frame has been moved from the host memory to transmit FIFO. When reset, the packet transmission's start will depend on the threshold value specified in CR6<15:14>. Reserved Reserved In external MII mode, use this bit to enable or disable internal PHY See page 56 "7.8 External MII Interface" for details. Reserved One Packet Mode When this bit is set, only one packet is stored at TX FIFO Final Version: DM9102D-DS-F01 May 10, 2006 25 15:14 TSB 0,RW Threshold Bits These bits are set together with CR6 [22] and will decide the exact FIFO threshold level. The packet transmission will start after the data in the FIFO exceeds the threshold value. Bit 22 Bit15 Bit14 Threshold 0 0 0 128 bytes 0 0 1 256 bytes 0 1 0 512 bytes 0 1 1 1024 bytes 1 0 0 64 bytes 1 0 1 128 bytes 1 1 0 192 bytes 1 1 1 256 bytes Transmit Start/Stop Command When set, the transmit process will begin by fetching the transmit descriptor for available packet data to be transmitted (running state). If the fetched descriptor is owned by the host, transmit process will enter the suspend state and transmit buffer unavailable (CR5<2>) is set. Otherwise it will begin to move data from host to FIFO and transmit out after reaching threshold value. When reset, the transmit process is placed in the stopped state after completing the transmission of the current frame. Force Collision Mode When set, the transmission process is forced to be the collision status. Meaningful only in the internal loop-back mode. Loop-back Mode These bits decide two loop-back modes, MAC and PHY, besides normal operation. These loop-back modes expect transmitted data back to receive path and ignore collision detection. Bit11 0 0 1 1 Bit10 0 1 0 1 Loop-back Mode Normal Internal loop-back Internal PHY digital loop-back Internal PHY analog loop-back 13 TXSC 0,RW 12 FCM 0,RW 11:10 LBM 0,RW 9 FDM 0,RW 8 7 Reserved PAM 0,RO 0,RW 6 PM 0,RW 5 Reserved 0,RO Full-duplex Mode When internal PHY is selected, this bit is the status of full-duplex mode of internal PHY. When external PHY is selected, set this bit to make the MAC of the DM9102D operate in the full-duplex mode. Must be Zero Pass All Multicast When set, any packet with a multicast destination address is received by the DM9102D. The packet with a physical address will also be filtered based on the filter mode setting Promiscuous Mode When set, any incoming valid frame is received by the DM9102D, and no matter what the destination address is. The DM9102D is initialized to this mode after reset operation. Must be Zero 26 Final Version: DM9102D-DS-F01 May 10, 2006 4 IAFM 0,RO 3 PBF 0,RW 2 HOFM 0,RO 1 RXRC 0,RW 0 HPFM 0,RO Inverse Address Filtering Mode It is set to indicate the DM9102D operate in Inverse filtering mode. This is a read only bit and decoded from the setup frame of TDES1 bit 28 and bit 22. Pass Bad Frame When set, the DM9102 is indicated that receiving the bad frames, including runt packets and truncated frames, is caused by the FIFO overflow. The bad frame also has to pass the address filtering if the DM9102D is not set in promiscuous mode. Hash-only Filter Mode It is set to indicate the DM9102D operate in Hash-only filtering mode. This is a read only bit and decoded from the setup frame of TDES1 bit 28 and bit 22. Receive Start/Stop Command When set, receive process will begin by fetching the receive descriptor for available buffer to store the new-coming packet (placed in the running state). If the fetched descriptor is owned by the host (no descriptor is owned by the DM9102D), the receive process will enter the suspend state and receive buffer unavailable CR5<7> sets. Otherwise it runs to wait for the packet's incoming. When reset, receive process is placed in the stopped state after completing the reception of the current frame. Hash/Perfect Filter Mode It is set to indicate the DM9102D operate in Hash-only or Hash filtering mode and it is cleared to indicate the DM9102D operate in Perfect filtering mode. This is a read only bit and decoded from the setup frame of TDES1 bit 28 and bit 22. 6.2.8 Interrupt Mask Register (CR7) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 16 Name NISE Default 0,RW 15 AISE 0,RW 14 13 Reserved SBEE 0,RO 0,RW 12 LINKE 0,RW 11:10 Reserved 0,RO Description Normal Interrupt Summary Enable This bit is set to enable the interrupt for Normal Interrupt Summary. Normal interrupt includes three conditions: CR5<0> - TXCI: Transmit Complete Interrupt CR5<2> - TXDU: Transmit Buffer Unavailable CR5<6> - RXCI: Receive Complete Interrupt Abnormal Interrupt Summary Enable This bit is set to enable the interrupt for Abnormal Interrupt Summary. Abnormal interrupt includes all interrupt conditions as shown below, excluding Normal Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5), RXDU(bit7), RXPS(bit8), RXWT(bit9), SBE(bit13). Reserved System Bus Error Enable When set together with CR7<15>, CR5<13>, it enables the interrupt for System Bus Error. The type of system bus error is shown in CR5<24:23>. Link Change Interrupt Enable When this bit and CR7<16>, CR5<12> are set together, it will enable the interrupt of link status changed condition. Reserved Final Version: DM9102D-DS-F01 May 10, 2006 27 9 RXWTE 0,RW 8 RXPSE 0,RW 7 RXDUE 0,RW 6 RXCIE 0,RW 5 TXFUE 0,RW 4 3 Reserved TXJTE 0,RO 0,RW 2 TXDUE 0,RW 1 TXPSE 0,RW 0 TXCIE 0,RW Receive Watchdog Timer Expired Enable When this bit and CR7<15>, (CR5<9> are set together, it enable the interrupt of the condition of the receive watchdog timer expired. Receive Process Stopped Enable When set together with CR7<15> and CR5<8>. This bit is set to enable the interrupt of receive process stopped condition. Receive Buffer Unavailable Enable When this bit and CR7<15>, CR5<7> are set together, it will enable the interrupt of receive buffer unavailable condition. Receive Complete Interrupt Enable When this bit and CR7<16>, CR5<6> are set together, it will enable the interrupt of receive process complete condition. Transmit FIFO Underrun Enable When set together with CR7<15>, CR5<5>, it will enable the interrupt of transmit FIFO underrun condition. Reserved Transmit Jabber Expired Enable When this bit and CR7<15>, CR5<3> are set together, it enables the interrupt of transmit Jabber Timer Expired condition. Transmit Buffer Unavailable Enable When this bit and CR7<16>, CR5<2> are set together, the interrupt of transmit buffer unavailable is enabled. Transmit Process Stopped Enable When this bit is set together with CR7<15> and CR5<1>, it will enable the interrupt of the transmit process to stop. Transmit Complete Interrupt Enable When this bit and CR7<16>, CR5<0> are set, the transmit interrupt is enabled. 6.2.9 Statistical Counter Register (CR8) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 31 30:25 24:17 Name ROCO Reserved RXDU Default 0,RO/C 0,RO 0,RO/C 16 RXPS 0,RO/C 15:7 6:0 Reserved RXCI 0,RO 0,RO/C Description Receive Overflow Counter Overflow This bit is set when the Purged Packet Counter (RXDU) has an overflow condition. Reserved Receive Purged Packet Counter This is a statistic counter to indicate the purged received packet counts upon FIFO overflow. Receive Missed Counter Overflow This bit is set when the Receive Missed Frame Counter (RXCI) has an overflow condition. Reserved Receive Missed Frame Counter This is a statistic counter to indicate the Receive Missed Frame Count when there is a host buffer unavailable condition for receive process. 6.2.10 Management Access Register (CR9) 28 Final Version: DM9102D-DS-F01 May 10, 2006 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 31 30 29 28:27 26 25 24 23 22 21 20 19 18 Name MDIX MFUN LEDM Reserved FDX LNK100 LNK10 RSTPHY Reserved LES RLM MDIN MRW Default 0,RO 0,RO 0,RO 0,RO X,RO X,RO X,RO 0,RW 0,RO 0,RO 0,RW 0,RO 0,RW 17 MDOUT 0,RW 16 MDCLK 0,RW 15:12 11 10:8 7:4 3 Reserved ERS Reserved Reserved CRDOUT 1000,RO 0,RW 011,RW FH,RO 0,RW Description Status of disable HP Auto-MDIX function Multi-function strap pin status LED mode strap pin status Reserved Full-duplex status of internal PHY. 100M link status of internal PHY. 10M link status of internal PHY PHY Reset Write 1 to this bit will reset internal PHY. Reserved Load EEPROM status It is set to indicate the load of EEPROM is in progress. Reload EEPROM Set to reload the content of EEPROM. MII Management Data_In This is a read-only bit to indicate the MDIO input data, when bit 18 MRW is set. MII Management Read/Write Mode Selection This bit defines the Read/Write Mode for PHY MII management register access. 1 for read and 0 for write. MII Management Data_Out This bit is used to generate the output data signal for PHY MII management register access. MII Management Clock This bit is used to generate the output clock signal for PHY MII management register access. Reserved. EEPROM Selected This bit is used to enable EEPROM access. Reserved Reserved Data_Out from EEPROM This bit reflects the status of EEDI pin when the EEPROM access is enabled. Data_In to EEPROM This bit maps to EEDO pin when the EEPROM access is enabled. Clock to EEPROM This bit maps EECK pin when the EEPROM access is enabled Chip_Select to EEPROM This bit maps to EECS pin when the EEPROM access is enabled 2 1 0 CRDIN CRCLK CRCS 0,RW 0,RW 0,RW 6.2.11 PHY Status Register (CR12) Final Version: DM9102D-DS-F01 May 10, 2006 29 Bit 31:9 8:4 3:0 Name Reserved Reserved PHYST Default FFFFFFH, RO 0,RO XXXX ,RW Description Reserved Reserved PHY Status bit 3:Internal PHY Link status (the same as bit2 of PHY Register) bit 2:Full-duplex bit 1:Speed 100Mbps link bit 0:Speed 10Mbps link 30 Final Version: DM9102D-DS-F01 May 10, 2006 6.2.12 Sample Frame Access Register (CR13) (reference to section 7.5 Power Management) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register TxFIFO RxFIFO DiagReset General definition Transmit FIFO access port Receive FIFO access port General reset for diagnostic pointer port bit8 ~ 3 32H 35H 38H R/W R/W R/W W 6.2.13 Sample Frame Data Register (CR14) (reference to section 7.5 Power Management) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6.2.14 Watchdog and Jabber Timer Register (CR15) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 31 30 29 28 27 26:15 14 Name TXSUMC IPSUM TCPSUM UDPSUM RXSUM Reserved TXP0 Default 0,WO 0,WO 0,WO 0,WO 0,WO 0,RO 0,RW 13 TXPF 0,RW 12:11 10 9 8 7 6 Reserved FLCE RXPS Reserved RXPCS VLAN 0,RO 0,RW 0,R/C 0,RO 0,RO 0,RW Description in transmit, generate IP/TCP/UDP chksum depend-on TX desc. control in transmit, generate IP chksum to all packets in transmit, generate TCP chksum to all packets in transmit, generate UDP chksum to all packets In receiving, report IP/TCP/UDP checksum status to RDES0 Reserved Transmit pause packet Set to transmit pause packet with pause timer = 0000h, this bit will be cleared if the pause packet had transmitted. Transmit pause packet Set to transmit pause packet with pause timer = FFFFh, this bit will be cleared if the pause packet had transmitted. Reserved Flow Control Enable Set to enable the decode of the pause packet. The latched status of the decode of the pause packet. Reserved. It is set to indicate that the current pause timer of pause packet is not down count to zero yet. VLAN length Capability Enable It is set to enable the VLAN length mode and will not report the frame_too_long bit status to RDES0 if receive packet size under 1526-byte. 31 Final Version: DM9102D-DS-F01 May 10, 2006 5 4 3:1 0 Reserved TWDE Reserved TJE 0,RO 0,RW 0,RO 0,RW Reserved Watchdog Timer Disable When set, the Watchdog Timer is disabled. Otherwise it is enabled. Reserved Transmit Jabber Disable When set, the transmit Jabber is disabled. Otherwise it is enabled. 6.3 PHY Management Register Set Offset 0 1 2 3 4 5 6 7-15 10H 11H 12H 13H 14H Others Register Name BMCR BMSR PHYIDR1 PHYIDR2 ANAR ANLPAR ANER Reserved DSCR DSCSR 10BTCSR PWDOR MDIX Reserved Description Default value after reset Basic Mode Control Register 3100H Basic Mode Status Register 7849H PHY Identifier Register #1 0181H PHY Identifier Register #2 B8A0H Auto-Negotiation Advertisement Register 01E1H Auto-Negotiation Link Partner Ability Register 0000H Auto-Negotiation Expansion Register 0000H Reserved 0000H DAVICOM Specified Configuration Register 0414H DAVICOM Specified Configuration/Status Register F210H 10BASE-T Configuration/Status Register 7800H Power Down Control Register 0000H Aoto-MDI/MDIX Control Register 0000H Reserved for future use, do not read/write to these 0000H Registers Key to Default In the register description that follows, the default column takes the form: 32 Final Version: DM9102D-DS-F01 May 10, 2006 6.3.1 Basic Mode Control Register (BMCR) - 0 Bit Name Default Description 15 Reset 0, RW/SC Reset: 1=Software reset 0=Normal operation This bit resets the status and controls the PHY registers of the DM9102D to their default states. This bit, which is self-clearing, will keep its value until the reset process is completed 14 Loopback 0, RW Loopback: 1=Loop-back enabled 0=Normal operation When in 100Mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data to the MAC. 13 Speed Selection 1, RW Speed Select: 1=100Mbps 0=10Mbps Link speed may be selected either by this bit or by Auto-negotiation. When Auto-negotiation is enabled and bit 12 is set, this bit will reflect Autonegotiation selected media type. 12 Auto-negotiation 1, RW Auto-negotiation Enable: Enable 1= Auto-negotiation enabled: bit 8 and 13 will report Auto-negotiation status 0= Auto-negotiation disabled: bit 8 and 13 will determine the link speed and duplex mode 11 Power Down 0, RW Power Down: Setting this bit will power down the internal PHY except crystal / oscillator circuit. 1=Power Down 0=Normal Operation 10 Reserved 0,RO Reserved. Write as 0, ignore on read. 9 Restart 0,RW/SC Restart Auto-negotiation: Auto-negotiation 1= Restart Auto-negotiation. Re-initiates the Auto-negotiation process. When Auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep its value until Auto-negotiation is initiated by the DM9102D. The operation of the Auto-negotiation process will not be affected by the management entity that clears this bit. 0= Normal Operation 8 Duplex Mode 1,RW Duplex Mode: 1= Full Duplex operation. Duplex selection is allowed when Auto-negotiation is disabled (bit 12 of this register is cleared). With Auto-negotiation enabled, this bit reflects the duplex capability selected by Auto-negotiation. 0= Normal operation 7 Collision Test 0,RW Collision Test: 1= Collision Test enabled. When set in half duplex mode, the DM9102D will enter collision state if packet transmission is in progress. 0= Normal Operation 6:0 Reserved <0000000>, Reserved. Write as 0, ignore on read RO 6.3.2 Basic Mode Status Register (BMSR) - 1 Final Version: DM9102D-DS-F01 May 10, 2006 33 Bit 15 Name 100BASE-T4 Default 0,RO/P Description 100BASE-T4 Capable: 1=DM9102D is able to perform in 100BASE-T4 mode. 0=DM9102D is not able to perform in 100BASE-T4 mode. 100BASE-TX FULL DUPLEX CAPABLE: 1= DM9102D is able to perform 100BASE-TX in Full Duplex mode. 0= DM9102D is not able to perform 100BASE-TX in Full Duplex mode. 100BASE-TX Half Duplex Capable: 1=DM9102D is able to perform 100BASE-TX in Half Duplex mode. 0=DM9102D is not able to perform 100BASE-TX in Half Duplex mode. 10BASE-T Full Duplex Capable: 1=DM9102D is able to perform 10BASE-T in Full Duplex mode. 0=DM9102D is not able to perform 10BASE-T in Full Duplex mode. 10BASE-T Half Duplex Capable: 1=DM9102D is able to perform 10BASE-T in Half Duplex mode. 0=DM9102D is not able to perform 10BASE-T in Half Duplex mode . Reserved: Write as 0, ignore on read MII Frame Preamble Suppression: 1=PHY will accept management frames with preamble suppressed. 0=PHY will not accept management frames with preamble suppressed. Auto-negotiation Complete: 1=Auto-negotiation process is completed. 0=Auto-negotiation process is not completed. Remote Fault: 1= Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is DM9102D specific implementation. This bit will set after the RF bit in the ANLPAR (bit 13, register address 05) is set 0= No remote fault condition detected Auto Configuration Ability: 1=DM9102D is able to perform Auto-negotiation 0=DM9102D is not able to perform Auto-negotiation Link Status: 1=Valid link established (for either 10Mbps or 100Mbps operation) 0=Link not established The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the Link Status bit to be cleared and remain cleared until it is read via the management interface Jabber Detect: 1=Jabber condition detected 0=No jabber This bit is implemented with a latching function. Jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9102D reset. This bit works only in 10Mbps mode Extended Capability: 1=Extended register capability 0=Basic register capability only 14 100BASE-TX Full Duplex 100BASE-TX Half Duplex 10BASE-T Full Duplex 10BASE-T Half Duplex Reserved MF Preamble Suppression Auto-negotiation Complete Remote Fault 1,RO/P 13 1,RO/P 12 1,RO/P 11 1,RO/P 10:7 6 0000,RO 1,RW 5 0,RO 4 0,RC/LH 3 Auto-negotiation Ability Link Status 1,RO/P 2 0,RC/LL 1 Jabber Detect 0,RC/LH 0 Extended Capability 1,RO/P 6.3.3 PHY Identifier Register #1 (PHYIDR1) - 2 34 Final Version: DM9102D-DS-F01 May 10, 2006 The PHY Identifier Register#1 and Register#2 work together in a single identifier of the DM9102D. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E. Bit 15:.0 Name OUI_MSB Default Description <0181H>, OUI Most Significant Bits: RO/P This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of this register respectively. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bit 1 and 2) 6.3.4 PHY Identifier Register #2 (PHYIDR2) - 3 Bit Name Default Description 15:10 OUI_LSB <101110>, OUI Least Significant Bits: RO/P Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register respectively 9:.4 VNDR_MDL <001010>, Vendor Model Number: RO/P Six bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) 3:0 MDL_REV <0000>, Model Revision Number: RO/P Four bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 3) 6.3.5 Auto-negotiation Advertisement Register (ANAR) - 4 This register contains the advertised abilities of this DM9102D device as they will be transmitted to its link partner during Auto-negotiation. Bit Name Default Description 15 NP 0,RO/P Next Page Indication: 0=No next page available 1=Next page available The DM9102D has no next page, so this bit is permanently set to 0 14 ACK 0,RO Acknowledge: 1=Link partner ability data reception acknowledged 0=Not acknowledged The DM9102D's Auto-negotiation state machine will automatically control this bit in the outgoing FLP bursts and set it at the appropriate time during the Auto-negotiation process. Software should not attempt to write to this bit. 13 RF 0, RW Remote Fault: 1=Local Device senses a fault condition 0=No fault detected 12:11 Reserved 00, RW Reserved: Write as 0, ignore on read 10 FCS 0, RW Flow Control Support: 1=Controller chip supports flow control ability. 0=Controller chip doesn't support flow control ability. 9 T4 0, RW 100BASE-T4 Support: 1=100BASE-T4 is supported by the local device. 0=100BASE-T4 is not supported. The DM9102D does not support 100BASE-T4 so this bit is 0 permanently 8 TX_FDX 1, RW 100BASE-TX Full Duplex Support: 1=100BASE-TX Full Duplex is supported by the local device. 0=100BASE-TX Full Duplex is not supported. Final Version: DM9102D-DS-F01 May 10, 2006 35 7 TX_HDX 6 10_FDX 5 10_HDX 4:.0 Selector 100BASE-TX Support: 1=100BASE-TX is supported by the local device. 0=100BASE-TX is not supported. 1, RW 10BASE-T Full Duplex Support: 1=10BASE-T Full Duplex is supported by the local device. 0=10BASE-T Full Duplex is not supported. 1, RW 10BASE-T Support: 1=10BASE-T is supported by the local device. 0=10BASE-T is not supported. <00001>, Protocol Selection Bits: RW These bits contain the binary encoded protocol selector supported by this node. <00001> indicates that this device supports IEEE 802.3 CSMA/CD. 1, RW 6.3.6 Auto-negotiation Link Partner Ability Register (ANLPAR) - 5 This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit Name Default Description 15 NP 0, RO Next Page Indication: 1= Link partner, next page available 0= Link partner, no next page available 14 ACK 0, RO Acknowledge: 1=Link partner ability data reception acknowledged 0=Not acknowledged The DM9102D's Auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit. 13 RF 0, RO Remote Fault: 1=Remote fault is indicated by link partner. 0=No remote fault is indicated by link partner. 12:10 Reserved 000, RO Reserved: Write as 0, ignore on read 9 T4 0, RO 100BASE-T4 Support: 1=100BASE-T4 is supported by the link partner. 0=100BASE-T4 is not supported by the link partner. 8 TX_FDX 0, RO 100BASE-TX Full Duplex Support: 1=100BASE-TX Full Duplex is supported by the link partner. 0=100BASE-TX Full Duplex is not supported by the link partner. 7 TX_HDX 0, RO 100BASE-TX Support: 1=100BASE-TX Half Duplex is supported by the link partner. 0=100BASE-TX Half Duplex is not supported by the link partner. 6 10_FDX 0, RO 10BASE-T Full Duplex Support: 1=10BASE-T Full Duplex is supported by the link partner. 0=10BASE-T Full Duplex is not supported by the link partner. 5 10_HDX 0, RO 10BASE-T Support: 1=10BASE-T Half Duplex is supported by the link partner. 0=10BASE-T Half Duplex is not supported by the link partner. 4:0 Selector <00000>, Protocol Selection Bits: RO Link partner's binary encoded protocol selector 6.3.7 Auto-negotiation Expansion Register (ANER) - 6 Bit Name Default 15:5 Reserved 0, RO Reserved: 36 Description Final Version: DM9102D-DS-F01 May 10, 2006 Write as 0, ignore on read 4 PDF 0, RO/LH Local Device Parallel Detection Fault: PDF=1: A fault detected via parallel detection function. PDF=0: No fault detected via parallel detection function 0, RO Link Partner Next Page Able: LP_NP_ABLE=1: Link partner, next page available LP_NP_ABLE=0: Link partner, no next page 0,RO/P Local Device Next Page Able: NP_ABLE=1: DM9102D, next page available NP_ABLE=0: DM9102D, no next page DM9102D does not support this function, so this bit is always 0. 0, RC/LH New Page Received: A new link of code-word page received. This bit will be automatically cleared when the register (Register 6) is read by management. 0, RO Link Partner Auto-negotiation Able: A "1" in this bit indicates that the link partner supports Auto-negotiation. 3 LP_NP_ABLE 2 NP_ABLE 1 PAGE_RX 0 LP_AN_ABLE 6.3.8 DAVICOM Specified Configuration Register (DSCR) - 10H Bit Name Default Description 15 BP_4B5B 0,RW Bypass 4B5B Encoding and 5B4B Decoding 1 = 4B5B encoder and 5B4B decoder function bypassed 0 = Normal 4B5B and 5B4B operation 14 BP_SCR 0, RW Bypass Scrambler/Descrambler Function 1 = Scrambler and descrambler function bypassed 0 = Normal scrambler and descrambler operation 13 BP_ALIGN 0, RW Bypass Symbol Alignment Function 1 = Receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. Transmit functions (symbol encoder and scrambler) bypassed 0 = Normal operation 12:11 Reserved 0, RW Reserved 10 Reserved 1, RW Reserved 9:8 Reserved 0, RW Reserved 7 F_LINK_100 0, RW Force Good Link in 100Mbps: 1 = Force 100Mbps good link status 0 = Normal 100Mbps operation This bit is useful for diagnostic purposes. 6:5 Reserved 00,RW Reserved 4 RPDCTR_EN 1,RW Reduced Power Down Control Mode: This bit is used to enable automatic reduced power down 1 = Enable automatic reduced power down 0 = Disable automatic reduced power down 3 SMRST 0,RC Reset State Machine: When writes 1 to this bit, all state machines of PHY will be reset. This bit is self-clear after reset is completed. 2 MFPSC 1,RW MF Preamble Suppression Control: MII frame preamble suppression control bit 1 = MF preamble suppression bit on 0 = MF preamble suppression bit off Final Version: DM9102D-DS-F01 May 10, 2006 37 1 SLEEP 0,RW 0 RLOUT 0,RW Sleep Mode: Writing a 1 to this bit will cause PHY entering the Sleep mode and power down all circuit except oscillator and clock generator circuit. When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset. Remote Loop out Control: When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for testing bit error rate. 6.3.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 11H Bit Name Default Description 15 100FDX 1, RO 100M Full Duplex Operation Mode: After Auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation mode is a 100Mbps Full Duplex mode. The software can read bit[15:12] to see which mode is selected after Auto-negotiation. This bit is invalid when it is not in the Auto-negotiation mode. 14 100HDX 1, RO 100M Half Duplex Operation Mode: After Auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation mode is a 100Mbps Half Duplex mode. The software can read bit[15:12] to see which mode is selected after Auto-negotiation. This bit is invalid when it is not in the Auto-negotiation mode. 13 10FDX 1, RO 10M Full Duplex Operation Mode: After Auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation mode is a 10Mbps Full Duplex mode. The software can read bit[15:12] to see which mode is selected after Auto-negotiation. This bit is invalid when it is not in the Auto-negotiation mode. 10M Half Duplex Operation Mode: After Auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation mode is a 10Mbps Half Duplex mode. The software can read bit[15:12] to see which mode is selected after Auto-negotiation. This bit is invalid when it is not in the Auto-negotiation mode. Reserved: 12 10HDX 1, RO 11:10 9 8:4 3:0 Reserved Reserved PHYAD[4:0] ANMB[3:0] 00, RO 1, RW Reserved: Write as 0, ignore on read 00001, RW PHY Address Bit 4:0 0000, RO Auto-negotiation Monitor Bits: These bits are for debug only. The Auto-negotiation status will be written to these bits. 38 Final Version: DM9102D-DS-F01 May 10, 2006 b3 0 0 0 0 0 0 0 0 b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0 0 0 1 0 1 0 1 1000 In IDLE state Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detects signal_link_ready Parallel detects signal_link_ready fail Auto-negotiation completed successfully 6.3.10 10BASE-T Configuration/Status (10BTCSRCSR) - 12H Bit Name Default Description 15 Reserved 0, RO Reserved: Write as 0, ignore on read 14 LP_EN 1, RW Link Pulse Enable: 1=Transmission of link pulses enabled 0=Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation. 13 HBE 1,RW Heartbeat Enable: 1=Heartbeat function enabled 0=Heartbeat function disabled When the DM9102D is configured for Full Duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in Full Duplex mode). It must set to be 1. 12 SQUELCH 1, RW Squelch Enable 1 = normal squelch 0 = low squelch 11 JABEN 1, RW Jabber Enable: Enables or disables the Jabber function when the DM9102D is in 10BASE-T Full Duplex or 10BASE-T Transceiver Loopback mode 1= Jabber function enabled 0= Jabber function disabled 10 Reserved 0,RW Reserved 9:2 Reserved 0, RO Reserved 1 Reserved 0,RW Reserved 0 POLR 0, RO Polarity Reversed When this bit is set to 1, it indicates that the 10Mbps cable polarity is reversed. Final Version: DM9102D-DS-F01 May 10, 2006 39 6.3.11 Power Down Control Register (PWDOR) - 13H Bit Bit Name Default Description 15:9 Reserved 0, RO Reserved Read as 0, ignore on write 8 PD10DRV 0, RW Vendor powerdown control test 7 PD100DL 0, RW Vendor powerdown control test 6 PDchip 0, RW Vendor powerdown control test 5 PDcom 0, RW Vendor powerdown control test 4 PDaeq 0, RW Vendor powerdown control test 3 PDdrv 0, RW Vendor powerdown control test 2 PDedi 0, RW Vendor powerdown control test 1 PDedo 0, RW Vendor powerdown control test 0 PD10 0, RW Vendor powerdown control test * when selected , the powerdown value is control by Register 20.0 6.3.12 Auot-MDI/MDIX Control Register - 14H Bit 15:13 11:8 7 Description Reserved Reserved Read as 0, ignore on write MDI/MDIX,RO The polarity of MDI/MDIX value MDIX_CNTL 1: MDIX mode 0: MDI mode AutoNeg_dpbk 0,RW Auto-negotiation loopback 1: test internal digital auto-negotiation loopback 0: normal. Mdix_fix Value 0, RW MDIX_CNTL force value: When MDIX_DOWN = 1, MDIX_CNTL value depend on the register value. Mdix_do wn 0,RW MDIX Down Manual force MDI/MDIX. 0: Enable HP Auto-MDIX 1: Disable HP Auto-MDIX , MDIX_CNTL value depend on bit 5. Reserved 0,RW Reserved PD_value 0,RW Powerdown control value Decide the value of each field Register 13H. 1: powerdown 0: normal Bit Name Reserved Reserved Default 0,RW 0, RO 6 5 4 3:1 0 40 Final Version: DM9102D-DS-F01 May 10, 2006 7. Functional Description 7.1 System Buffer Management 7.1.1 Overview The data buffers for reception and the transmission of data reside in the host memory. They are addressd by the descriptor list that is also located in another region of the host memory. All actions for the buffer management are operated by the DM9102D in conjunction with the software driver. The data structures and processing algorithms are described in the following text. 7.1.2 Data Structure and Descriptor List There are two types of buffers that reside in the host memory, the transmit buffer and the receive buffer. The buffers are composed of many distributed regions in the host memory. They are linked together and controlled by the descriptor lists that reside in another region of the host memory. The descriptor list is a chain structure. The content of each descriptor includes pointer to the buffer, size of the buffer, command and status for the packet to be transmitted or received. Each descriptor list starts from the address setting of CR3 (receive descriptor base address) and CR4 (transmit descriptor base address). Refer to Figure 7-1. 7.1.3 Buffer Management -- Chain Structure Method As the Chain structure depicted below, each descriptor contains two pointers, one point to a single buffer and the other to the next descriptor chained. The first descriptor is chained to the last descriptor under host driver's control to form a looped chain. With this structure, a descriptor can be allocated anywhere in host memory and is chained to the next descriptor. own status not valid buffer address 1 next descriptor address buffer 1 length control Buffer 1 Descriptor 1 Buffer 1 Packet N Descriptor N Figure 7-1 7.1.4 Descriptor List: Buffer Descriptor Format (a). Receive Descriptor Format Each receive descriptor has four double word entries and may be read or written by the host or the DM9102D. The descriptor format is shown below with a detailed functional description. Final Version: DM9102D-DS-F01 May 10, 2006 41 31 OWN OWN 0 Status Control bits Buffer Address Next Descriptor Address Buffer Length RDES 0 RDES 1 RDES 2 RDES 3 Receive Descriptor Format RDES0: 31 OWN 30 AUN 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Frame Length ( FL ) Bit 31: OWN, Owner bit of received status 1=owned by DM9102, 0=owned by host This bit will be reset after packet reception is completed. The host will set this bit after received data is removed. 15 14 13 12 11 10 9 8 7 6 Bit 30: AUN, Received address unmatched. Bit 29-16: FL, Frame Length Frame length indicates total byte count of received packet. 5 4 3 2 1 CE 0 FOE ES DUE LBOM RF MF BD ED TLF LCS EFL FT RWT PLE AE This word-wide content includes status of received frame. They are loaded after the received buffer that belongs to the corresponding descriptor is full. All status bits are valid only when the last descriptor (End Descriptor) bit is set. Bit 15: ES, Error Summary It is set for the following error conditions: Descriptor Unavailable Error (DUE =1), Runt Frame (RF=1), Excessive Frame Length (EFL=1), Late Collision Seen (LCS=1), CRC error (CE=1), FIFO Overflow error (FOE=1). Valid only when ED is set. Bit 14: DUE, Descriptor Unavailable Error It is set when the frame is truncated due to the buffer unavailable. It is valid only when ED is set. Bit 13,12: LBOM, Loopback Operation Mode or IP/TCP/UDP checksum status If CR15 bit 27 is set, these two bits present the IP/TCP/UDP status: 0X -- IP checksum OK 1X --IP checksum FAIL X0 - TCP or UDP checksum OK X1 - TCP or UDP checksum FAIL ; otherwise these two bits show the received frame is derived from: 42 00 --- Normal 01 --- Internal loopback 10 --- Internal PHY digital loopback 11 --- Internal PHY analog loopback Bit 11: RF, Runt Frame It is set to indicate the received frame has the size smaller than 64 bytes. It is valid only when ED is set and FOE is reset. Bit 10: MF, Multicast Frame It is set to indicate the received frame has a multicast address. It is valid only when ED is set. Bit 9: BD, Begin Descriptor This bit is set for the descriptor indicating the start of a received frame. Bit 8: ED, End Descriptor This bit is set for descriptor to indicate the end of a received frame. Bit 7: EFL, Excessive Frame Length It is set to indicate the received frame length exceeds 1518 bytes. Valid only when ED is set. Final Version: DM9102D-DS-F01 May 10, 2006 Bit 6: LCS: Late Collision Seen It is set to indicate a late collision found during the frame reception. Valid only when ED is set. Bit 5: FT, Frame Type or IP packet If CR15 bit 27 is set, this bit present the flag that this is IP packet; otherwise it is set to indicate the received frame is the Ethernet-type. It is reset to indicate that the received frame is the EEE802.3type. Valid only when ED is set Bit 4: RWT, Receive Watchdog Time-Out or TCP packet If CR15 bit 27 is set, this bit present the flag that this is TCP packet; otherwise it is set to indicate the received watchdog time-out during the frame reception. CR5<9> will also be set. Valid only when ED is set. Bit 3: PLE, Physical Layer Error or UDP packet RDES1: Descriptor Status and Buffer Size 31 30 29 28 27 26 25 24 23 22 C E 21 ~ 11 If CR15 bit 27 is set, this bit present the flag that this is UDP packet; otherwise it is set to indicate a physical layer error found during the frame reception. Bit 2: AE, Alignment Error It is set to indicate the received frame ends with a non-byte boundary. Bit 1: CE, CRC Error It is set to indicate the received frame ends with a CRC error. Valid only when ED is set. Bit 0: FOE, FIFO Overflow Error This bit is valid only when End Descriptor is set. (ED = 1). It is set to indicate a FIFO overflow error happens during the frame reception. 10 ~ 0 Buffer Length Bit 24: Must be 1. Bit 10-0: Buffer Length Indicates the size of the buffer. RDES2: Buffer Starting Address Indicates the physical starting address of buffer. This address must be double word aligned. 31 Buffer Address 0 RDES3: Next descriptor Address Indicates the physical starting address of the chained descriptor under the Chain descriptor structure. This address must be eight-word aligned. 31 Next descriptor Address 0 (b). Transmit Descriptor Format Each transmit descriptor has four double word content and may be read or written by the host or by the DM9102D. The descriptor format is shown below with detailed description Final Version: DM9102D-DS-F01 May 10, 2006 43 31 OWN OWN 0 Status Control bits Buffer Address Next Descriptor Address Buffer Length TDES0 TDES1 TDES2 TDES3 Transmit Descriptor Format TDES0: Owner Bit with Transmit Status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OWN Bit 31: OWN, 1=owned by DM9102D, 0=owned by host, this bit should be set when the transmitting buffer is filled with data and ready to be transmitted. It will be reset by DM9102D after transmitting the whole data buffer. 15 14 TX 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ES JT LOC NC LC EC 0 CC 0 FUE DF This word wide content includes status of transmitted frame. They are loaded after the data buffer that belongs to the corresponding descriptor is transmitted. Bit 15: ES, Error Summary It is set for the following error conditions: Transmit Jabber Time-out (TXJT=1), Loss of Carrier (LOC=1), No Carrier (NC=1), Late Collision (LC=1), Excessive Collision (EC=1), FIFO Underrun Error (FUE=1). Bit 14: TXJT, Transmit Jabber Time Out It is set to indicate the transmitted frame is truncated due to transmit jabber time out condition. The transmit jabber time out interrupt CR5<3> is set. Bit 11: LOC, Loss of Carrier It is set to indicate the loss of carrier during the frame transmission. It is not valid in internal loopback mode. Bit 10: NC, No Carrier 44 It is set to indicate that no carrier signal from transceiver is found. It is not valid in internal loopback mode. Bit 9: LC, Late Collision It is set to indicate a collision occurs after the collision window of 64 bytes. Not valid if FUE is set. Bit 8: EC, Excessive collision It is set to indicate that the transmission is aborted due to 16 excessive collisions. Bit 7: Reserved This bit is 0 when read. Bits 6-3: CC, Collision Count These bits show the number of collision before transmission. Not valid if excessive collision bit is also set. Bit 2: Reserved This bit is 0 when read. Final Version: DM9102D-DS-F01 May 10, 2006 Bit 1: FUE, FIFO Underrun Error It is set to indicate that the transmission aborted due to transmit FIFO underrun condition. Bit 0: DF, Deferred It is set to indicate that the frame is deferred before ready to transmit. TDES1: Transmit buffer control and buffer size 31 CI 30 ED 29 28 27 26 25 /// 24 CE 23 22 21 ~ 11 10 ~ 0 BD FMB1 SETF CAD PD FMB0 Buffer Length Bit 31: CI, Completion Interrupt It is set to enable transmit interrupt after the present frame has been transmitted. It is valid only when TDES1<30> is set or when it is a setup frame. Bit 30: ED, Ending Descriptor It is set to indicate the pointed buffer contains the last segment of a frame. Bit 29: BD, Begin Descriptor It is set to indicate the pointed buffer contains the first segment of a frame. Bit 28: FMB1, Filtering Mode Bit 1 This bit is used with FMB0 to indicate the filtering type when the present frame is a setup frame. Bit 27: SETF, Setup Frame It is set to indicate the current frame is a setup frame. Bit 26: CAD, CRC Append Disable It is set to disable the CRC appending at the end of the transmitted frame. Valid only when TDES1<29> is set. Bit 24: CE, Chain Enable Must be "1". Bit 23: PD, Padding Disable This bit is set to disable the padding field for a packet shorter than 64 bytes. Bit 22: FMB0, Filtering Mode Bit 0 This bit is used with FMB1 to indicate the filtering type when the present frame is a setup frame. FMB1 FMB0 Filtering Type 0 0 Perfect Filtering 0 1 Hash Filtering 1 0 Inverse Filtering 1 1 Hash-Only Filtering. Bit 21: IP Packet Checksum Generation This bit is set to enable the IP packet checksum generation, if per-packet checksum in CR15 bit 31 is enabled Bit 20: TCP Packet Checksum Generation This bit is set to enable the TCP packet checksum generation, if per-packet checksum in CR15 bit 31 is enabled. Bit 19: UDP Packet Checksum Generation This bit is set to enable the UDP packet checksum generation, if per-packet checksum in CR15 bit 31 is enabled. Bit 10-0: Buffer 1 length Indicates the size of buffer in Chain type structure. TDES2: Buffer Starting Address indicates the physical starting address of buffer. 31 Buffer Address 1 0 TDES3: Address indicates the next descriptor starting address Indicates the physical starting address of the chained descriptor under the Chain descriptor structure. This address must be eight-word alignment. Final Version: DM9102D-DS-F01 May 10, 2006 45 31 Buffer Address 2 0 46 Final Version: DM9102D-DS-F01 May 10, 2006 7.2 Initialization Procedure After hardware or software reset, transmit and receive processes are placed in the state of STOP. The DM9102D can accept the host commands to start operation. The general procedure for initialization is described below: (1) Read/write suitable values for the PCI configuration registers. (2) Write CR3 and CR4 to provide the starting address of each descriptor list. (3) Write CR0 to set global host bus operation parameters. (4) Write CR7 to mask causes of unnecessary interrupt. (5) Write CR6 to set global parameters and start both receive and transmit processes. Receive and transmit processes will enter the running state and attempt to acquire descriptors from the respective descriptor lists. (6) Wait for any interrupt. 7.2.1 Data Buffer Processing Algorithm The data buffer process algorithm is based on the cooperation of the host and the DM9102D. The host sets CR3 (receive descriptor base address) and CR4 (transmit descriptor base address) for the descriptor list initialization. The DM9102D will start the data buffer transfer after the descriptor polling and get the ownership. For detailed processing procedure, please see below. Stop State 7.2.2 Receive Data Buffer Processing Refer to Figure 7-2. The DM9102D always attempts to acquire an extra descriptor in anticipation of the incoming frames. Any incoming frame size covers a few buffer regions and descriptors. The following conditions satisfy the descriptor acquisition attempt: When start/stop receive sets immediately after being placed in the running state. When the DM9102D begins writing frame data to a data buffer pointed to by the current descriptor and the buffer ends before the frame ends. When the DM9102D completes the reception of a frame and the current receiving descriptor is closed. When receive process is suspended due to no free buffer for the DM9102D and a new frame is received. When receive polling demand is issued. After acquiring the free descriptor, the DM9102D processes the incoming frame and places it in the acquired descriptor's data buffer. When the whole received frame data has been transferred, the DM9102D will write the status information to the last descriptor. The same process will repeat until it encounters a descriptor flagged as being owned by the host. If this occurs, receive process enters the suspended state and waits the host to service Stop Receive Command or Reset Command Start Receive Command or Receive Poll Command Descriptor Access New Frame Coming or Receive Poll Command Receive Buffer Unavailabl Buffer Full Buffer Available ( OWN bit = 1 ) FIFO Threshold Reached Suspended Data Transfer Frame Fully Received Write Status Buffer not Receive Buffer Management State Transition Figure 7-2 Final Version: DM9102D-DS-F01 May 10, 2006 47 7.2.3 Transmit Data Buffer Processing Refer to Figure 7-3. When start/stop transmit command is set and the DM9102D is in running state, transmit process polls transmit descriptor list for frames requiring transmission. When it completes a frame transmission, the status related to the transmitted frame will be written into the transmit descriptor. If the DM9102D detects a descriptor flagged as owned by the host and no transmit buffers are available, transmit process will be suspended. While in the running state, transmit process can simultaneously acquire two frames. As transmit process completes copying the first frame, it immediately polls transmit descriptor list for the second frame. If the second frame is valid, transmit process copies the frame before writing the status information of the first frame. Both conditions will make transmit process suspend. (i) The DM9102D detects a descriptor owned by the host. (ii) A frame transmission is aborted when a locally induced error is detected. Under either condition, the host driver has to service the condition before the DM9102D can resume. Stop Transmit Command or Stop State Reset Command Start Transmit Command or Transmit Poll Command Descriptor Access Transmit Poll Transmit Buffer Unavailable ( Owned By Host ) Buffer Empty Suspended Buffer Available ( OWN bit = 1 ) Under FIFO Threshold Frame Fully Transmited Data Transfer Write Status Buffer not Empty Transmit Buffer Management State Transition Figure 7-3 48 Final Version: DM9102D-DS-F01 May 10, 2006 7.3 Network Function 7.3.1 Overview This chapter will introduce the normal state machine operation and MAC layer management like collision back-off algorithm. In transmit mode, the DM9102D initiates a DMA cycle to access data from a transmit buffer. It prefaces the data with the preamble, the SFD pattern, and it appends a 32-bit CRC. In receive mode, the data is de-serialized by receive mechanism and is fed into the internal FIFO. For detailed process, please see below. 7.3.2 Receive Process and State Machine a. Reception Initiation As a preamble being detected on receive data lines, the DM9102D synchronizes itself to the data stream during the preamble and waits for the SFD. The synchronization process is based on byte boundary and the SFD byte is 10101011. If the DM9102D receives a 00 or a 11 after the first 8 preamble bits and before receiving the SFD, the reception process will be terminated. b. Address Recognition After initial synchronization, the DM9102D will recognize the 6-byte destination address field. The first bit of the destination address signifies whether it is a physical address (=0) or a multicast address (=1). The DM9102D filters the frame based on the node address of receive address filter setting. If the frame passes the filter, the subsequent serial data will be delivered into the host memory. c. Frame Decapsulation The DM9102D checks the CRC bytes of all received frames before releasing the frame along with the CRC to the host processor. 7.3.3 Transmit Process and State Machine a. Transmission Initiation Once the host processor prepares a transmit descriptor for the transmit buffer, the host processor signals the DM9102D to take it. After the DM9102D has been notified of this transmit list, the DM9102D will start to move the data bytes from the host memory to the internal transmit FIFO. When the transmit FIFO is adequately filled to the programmed threshold level, or when there is a full frame buffered into the transmit FIFO, the DM9102D begins to encapsulate the frame. The transmit encapsulation is performed by the transmit state machine, which delays the actual transmission onto the network until the network has been idle for a minimum inter frame gap time. b. Frame Encapsulation The transmit data frame encapsulation stream consists of two parts: Basic frame beginning and basic frame end. The former contains 56 preamble bits and SFD, the later, FCS. The basic frame read from the host memory includes the destination address, the source address, the type/length field, and the data field. If the data field is less than 46 bytes, the DM9102D will pad the frame with pattern up to 46 bytes. c. Collision When concurrent transmissions from two or more nodes occur (termed; collision), the DM9102D halts the transmission of data bytes and begins a jam pattern consisting of AAAAAAAA. At the end of the jam transmission, it begins the backoff wait time. If the collision was detected during the preamble transmission, the jam pattern is transmitted after completing the preamble. The backoff process is called truncated binary exponential backoff. The delay is a random integer multiple of slot times. The number of slot times of delay before the Nth retransmission attempt is chosen as a uniformly distributed random integer in the range: 0 r < 2k k = min ( n, N ) and N=10 7.3.4 Physical Layer Overview The DM9102D supports 100Mbps and 10Mbps operation. It provides a direct interface either to Unshielded Twisted Pair cable UTP5 for 100BASE-TX fast Ethernet, or UTP5/UTP3 cable for 10BASE-T Ethernet. In physical level operation, it consists of the following functions: PCS: 4B5B encode/decode, scramble/de-scramble, and data serialize/parallelize NRZ/NRZI, MLT-3 encoder/decoder and driver MANCHESTER encoder/decoder 10BASE-T filter, driver/receiver, and MANCHESTER encoder/decoder Auto. MDI/MDIX detection Final Version: DM9102D-DS-F01 May 10, 2006 49 7.4 Serial Management Interface The serial management interface is used to obtain and control the status of PHY management register set through the internal MDC and MDIO signals, which is control by CR9 bits 19:16. The Management Data Clock (MDC) is equipped with a maximum clock rate of 2.5MHz. In read/write operation, the management data frame is 64-bit long start with 32 contiguous logic one bits (preamble) synchronization clock cycles on MDC. The Start of Frame Delimiter (SFD) is indicated by a <01> pattern followed by the operation code (OP):<10> indicates Read operation and <01> indicates Write operation. Following the OP Code is the 5-bit PHY Address field that is fixed to 00001b. For read operation, a 2-bit turnaround (TA) filing between Register Address field and Data field is provided for MDIO to avoid contention. "Z" stands for the state of high impedance. Following turnaround time, a 16-bit data is read from or written onto management registers. 7.4.1 Management Interface - Read Frame Structure MDC MDIO Read 32 "1"s Idle Preamble 0 SFD 1 1 0 A4 A3 PHY Address Write A0 R4 R3 R0 Z 0 D15 D14 Data Read // D1 D0 Idle // Op Code Register Address Turn Around 7.4.2 Management Interface - Write Frame Structure MDC MDIO Write 32 "1"s Idle Preamble 0 SFD 1 0 1 A4 A3 PHY Address A0 R4 R3 R0 1 0 D15 D14 Data D1 D0 Idle Op Code Register Address Write Turn Around 50 Final Version: DM9102D-DS-F01 May 10, 2006 7.5 Power Management 7.5.1 Overview The DM9102D supports power management mechanism. It complies with the ACPI Specification Rev 1.0, the Network Device Class Power Management Specification Rev 1.0, and the PCI Bus Power Management Interface Specification Rev 1.0. In addition, it also supports the Wake-On LAN (WOL) which is the feature of the AMD's Magic PacketTM technology. With this function, it can wakeup a remote sleeping station. 7.5.2 PCI Function Power Management States The DM9102D supports PCI function power states D0, D3(hot), D3(cold), and does not support D1, D2 states. In addition, PCI signals PME# (power management event, open drain) to pin A19 of the standard PCI connector. D0: normal & fully functional state D3 (hot): For controller, configuration space, that can be accessed and wake up on LAN circuit, can be enabled. PME# operational circuit is active, full function is supported to detect the wake up Frame & Link status. Because of functions in D3(hot) must respond to configuration space accesses as long as power and clock are supplied so that they can be returned to D0 state by software. D3 (cold): If Vcc is removed from a PCI device, all of its PCI functions transition immediately to D3(cold), no bus transaction is active without pci_clk condition and wake up on LAN operation should be alive. PME# operational circuit is active. Full function is supported under auxiliary power to detect the magic packet & Link status. When power restored, PCI RST# must be asserted and functions will return to D0 with a full PCI Spec. 2.2 compliant power-on reset sequence. The power required in D3(cold) must be provided by some auxiliary power source. 7.5.3 The Power Management Operation It complies with the PCI Bus Power Management Interface Specification Rev. 1.0. The Power Management Event (PME#) signal is an optional open drain, active low signal that is intended to be driven low by a PCI function to request a change in its current power management state and/or to indicate that a power management event has occurred. The PME# signal has been assigned to pin A19 of the standard PCI Connector configuration. The assertion and de-assertion of PME# is asynchronous to the PCI clock. Final Version: DM9102D-DS-F01 May 10, 2006 Software will enable its use by setting the PME_En bit in the PMCSR (write 1 to PMCSR<8>). When a PCI function generates or detects an event that requires the system to change its power state, the function will assert PME#. It must continue to assert PME# until software either clears the PME_En bit (PMCSR<8> is set to 0) or clears the PME_Status bit in the PMCSR (write 1 to PMCSR<15>). DM9102D supports three main categories of network device wake up events specified in Network Device Class Power Management Rev1.0. That is, the DM9102D can monitor the network for a Link Change, Magic Packet or a Wake-up Frame and notify the system by generating PME# if any of the three events occurs. Programming the PCIUSR (offset = 40h) can select the PME# event, and writing 1 to PMCSR<15> will clear the PME#. a. Detect Network Link State Change Any link status change will set the wake up event. 1. Writes 1 into PMCSR<15>(54h) to clear previous PME# status 2. Writes 1 into PMCSR<8> to enable PME# function 3. Writes 1 into PCIUSR<29> to enable the link status change function b. Active Magic Packet Function It can be enabled by PCIUSR<27> or optionally enabled by EEPROM setting. The magic node address stored at node address table can use setup frame perfect address filtering mode or loading from EEPROM WORD 10~12 after power on . 1. Writes 1 into PMCSR<15> to clear previous PME status 2. Writes 1 into PMCSR<8> to enable PME# function 3. Writes 1 into PCIUSR<27> to enable magic packet function. c. Active the Sample Frame Function It can be enabled by PCIUSR<28>. Sample frame data and corresponding byte mask are loaded into transmit FIFO & receive FIFO before entering D3(hot). The software driver has to stop the TX/RX process before setting the sample frame and byte mask into the FIFO. Transmit & receive FIFO can be accessed from CR13 & CR14 by programming CR6<28:25> = 0011. 51 The operational sequence from D0 to D3 should be: Stop TX/RX process wait for entering stop state set test mode, CR6<28:25> = 0011 programming FIFO contents exit test mode enter D3 (hot) state The sample frame data comparison is completed when the received frame data has exceeded the programmed frame length or when the whole packet has been fully received. The operation procedure is shown below. CR13: Sample Frame Access Register Name General definition TxFIFO Transmit FIFO access port RxFIFO Receive FIFO access port DiagReset General reset for diagnostic pointer port In DiagReset port there are 7 bits: Bit 0: Clear TX FIFO write_ address to 0 Bit 1: Clear TX FIFO read_ address to 0 Bit 2: Clear RX FIFO write_ address to 0 Bit 3: Clear RX FIFO read_ address to 0 Bit8:3 32h 35h 38h Type R/W RW RW Bit 4: Reserved Bit 5: Set TX FIFO write_ address to 080H Bit 6: Set RX FIFO write_ address to 080H 52 Final Version: DM9102D-DS-F01 May 10, 2006 7.6 Sample Frame Programming Guide: 1. Enter the sample frame access mode: Set CR6<28:25>=0011 2.Reset the TX/RX FIFO, write pointer to offset 0: Write 38H to CR13<8:3> Write 01h to CR14 (reset) Write 00h to CR14 (clear) 3. Write the sample frame 0-3 data to RX FIFO: Write 35H to CR13<8:3> Write xxxxxxxxh to CR14 (Frame1~3 first byte) Write xxxxxxxxh to CR14 (Frame1~3 second byte) : : Repeat write until all frame data written to RX FIFO 4. Reset RX FIFO, write pointer to offset 080H: Write 38H to CR13<8:3> Write 40H to CR14 (reset) Write 00H to CR14 (clear) 5. Write the sample frame 4-7 to RX FIFO: Write 35H to CR13<8:3> Write xxxxxxxxh to CR14 (Frame4~7 first byte) Write xxxxxxxxh to CR14 (Frame4~7 second byte) : : Repeat write until all frame data written to RX FIFO 6. Write the sample frame 0-3 mask to TX FIFO: Write 32H to CR13<8:3> Write xxxxxxxxh to CR14 (Frame0~3 first mask byte) Write xxxxxxxxh to CR14 (Frame0~3 second mask byte) : : Repeat write until all frame mask which is written to TX FIFO 7. Reset TX FIFO, write pointer to offset 080H: Write 38H to CR13<8:3> Write 20H to CR14 (reset) Write 00H to CR14 (clear) 8. Write the sample frame 4-7 mask to TX FIFO: Write 32H to CR13<8:3> Write xxxxxxxxh to CR14 (Frame4~7 first mask byte) Write xxxxxxxxh to CR14 (Frame4~7 second mask byte) : : Repeat write until all frame mask is written to TX FIFO Final Version: DM9102D-DS-F01 May 10, 2006 53 7.7 EEPROM Overview The first 13 words of Configuration EEPROM are loaded into the DM9102D after power-on-reset for the settings of the power management, system ID and Ethernet address. The format of the EEPROM is as followed The format of EEPROM Field Name Subsystem Vendor ID Subsystem ID Reserved NCE and Auto_ load_ control PCI Vendor ID PCI Device ID PMCSR and PMC Reserved Ethernet Address 7.7.1 Subsystem ID Block Every card has a Subsystem ID to indicate the information of system vendor. The content will be transferred into the PCI configuration space 2CH. 7.7.2Vendor ID Vendor ID & Device ID can be set in EEPROM content & auto-loaded to PCI configuration register after reset.(default value = 1282H, 9102H) This function must be selectable for enable by Auto_ Load_ Control (word offset 04 bit[3:0] of EEPROM). Word Offset 0 1 2 4 5 6 7 8 10 Enable Word Size 1 1 2 1 1 1 1 2 3 7.7.4 Word Offset (04): New_ Capabilities_ Bit0: Directly mapping to bit20 (New Capabilities) of the PCICS If Bit9=1, Bit [12:10] mapping to bit [18:16] of the PCIPMR and Bit [15:13] mapping to bit [24:22] of the PCIPMR. 7.7.5 Word Offset (07): PMC 7 32 0 7.7.3 Word Offset (04): Auto_ Load_ Control Bit7~3: Directly mapping to bit[31:27] of the PCIPMR. Bit2~0: Directly mapping to bit[21,26:25] of the PCIPMR. 7.7.6 Word Offset (07): Control 7 43 0 Bit3~0: "1010" to enable auto-load of PCI Vendor_ ID & Device_ ID. Bit7~4: "1X1X" to enable auto-load of NCE, PME & PMC & PMCSR to PCI configuration space. Bit 4 and 6 are used to control the polarity and pulse mode of the WOL pin. If bit4 = 0, WOL is Active HIGH. If bit4=1, WOL is Active LOW If bit6 = 0, WOL is PULSE signal If bit6=1, WOL is LEVEL signal. Bit 15: Reserved Bit 14: Disable to power-down PHY if ISOLATE pin is low. Bit 13: Clear PMCSR[1:0] if RST# pin is low Bit 12: PME# is not pulse mode Bit 11: Set to disable the output of WOL pin. Bit 10: Set to disable the output of PME# pin. Bit 9: Set to enable the link change wake up event. Bit 8: Set to enable the Magic packet wake up event. 54 Final Version: DM9102D-DS-F01 May 10, 2006 7.7.7 Word Offset (10~12): Ethernet Address Address 0 = EEPROM Word 10 low byte Address 1 = EEPROM Word 10 high byte Address 2 = EEPROM Word 11 low byte 7.7.8 Example of DM9102D EEPROM Format Total Size: 128 Bytes Field Name Sub-Vendor ID Sub-Device ID Reserved1 Auto_Load_Control Address 3 = EEPROM Word 11 high byte Address 4 = EEPROM Word 12 low byte Address 5 = EEPROM Word 12 high byte Offset (Byte) Size (Bytes) 0 2 4 8 2 2 4 1 New_Capabilities_Enable (NCE) PCI Vendor ID PCI Device ID 9 10 12 1 2 2 Value Commentary (Hex) 1282H ID Block 9102H 00000000 00 Auto-load function definition: Bit 3~0 = 1010 Auto-Load PCI Vendor ID/Device ID enabled Bit 7~4 = 1x1x Auto-Load NCE, PMC/PMCSR enabled 00 Please refer to DM9102D Spec. 1282H 9102H If Auto-Load PCI Vendor ID/Device ID function disabled, the PCI Vendor ID/Device ID will use the default values (1282H, 9102H). Please refer to DM9102D Spec. Please refer to DM9102D Spec. Power Management Capabilities (PMC) Power Management Control/Status (PMCSR) Reserved2 IEEE Network Address Driver area 14 15 16 20 26 1 1 4 6 102 00 00 00 - Controller Info Header For software driver Final Version: DM9102D-DS-F01 May 10, 2006 55 7.8 External MII Interface DM9102D provides one external MII interface sharing with all the pins with Boot ROM interface. This external MII interface can be connected with external PHYceiver such as Home Networking PHYceiver or other future technology Test 1 (pin 37) Test 2 (pin 71) 0 1 Normal Operation 0 0 External MII mode 1 X Internal Test mode applications. This external MII interface can be set up by hardware and software. The setup methods are listed as below: Clkrun# (pin 36) X 0 X EECK (pin 79) X 0 X EEDO (pin 78) X 1/0 Note 1 X Note 1: External MII mode EEDO = 1(pulled high): only external PHY is selected. EEDO= 0(floating) & MII_ Mode = 1: Select external PHY EEDO = 0(float) & MII_ Mode = 0: Select internal PHY Where MII_ Mode is the bit 18 of CR6 7.8.1 The Sharing Pin Table (o): output, (i): input, (b): bi-direction Normal Operation Boot ROM interface TEST2=1 Pin 62 63 64 65 66 67 68 69 75 78 79 83 84 87 88 89 90 MD0/EEDI MD1 MD2 MD3 MD4 MD5 MD6 MD7 IDSEL2 EEDO EECK LED_MODE REQ2# TRF_LED FDX_LED SPD100_LED SPD10_LED External MII Interface External MII interface TEST2= 0 MII_MDIO/EEDI(b) MII_RXD2 (i) MII_RXD1 (i) MII_RXD0 (i) MII_RXDV (i) MII_RXER (i) MII_CRS (i) MII_RXCLK (i) MII_COL(i) MII_TXD0/EEDO(o) MII_TXD1/EECK (o) MII_TXEN(o) MII_TXCLK (i) MII_TXD2(o) MII_TXD3(o) MII_MDC(o) MII_RXD3(i) 56 Final Version: DM9102D-DS-F01 May 10, 2006 8. DC and AC Electrical Characteristics 8.1 Absolute Maximum Ratings ( 25C ) Symbol Parameter DVDD, AVDD Supply Voltage DVDD25,AVDD25 Supply Voltage VIN DC Input Voltage (VIN) VOUT DC Output Voltage (VOUT) Tc Case Temperature Range Tstg Storage Temperature Rang (Tstg) LT Lead Temp. (TL, Soldering, 10 sec.) LT Lead Temp. (TL, Soldering, 10 sec.) Min. -0.3 -0.3 -0.5 -0.3 0 -65 ----Max. 3.6 2.7 5.5 3.6 85 150 235 260 Unit V V V V C C C C Conditions DM9102DE DM9102DEP 8.2 Operating Conditions Symbol Parameter DVDD,AVDD Supply Voltage DVDD25,AVDD25 Supply Voltage Tc Case Temperature Ta Ambient Temperature PD 100BASE-TX (Power 100BASE-TX IDLE Dissipation) 10BASE-T TX 10BASE-T IDLE Auto-negotiation Power Reduced Mode (without cable) Power-Down Mode Min. 3.135 2.375 0 0 --------------- Max. 3.465 2.625 85 70 93 91 99 40 51 29 12 Unit V V C C mA mA mA mA mA mA mA Conditions @Ta=0 ~ 7 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Final Version: DM9102D-DS-F01 May 10, 2006 57 8.3 DC Electrical Characteristics (0C Transmitter VTD100 100TX+/- Differential Output Voltage VTD10 10TX+/- Differential Output Voltage ITD100 100TX+/- Differential Output Current ITD10 10TX+/- Differential Output Current 1.9 4.4 19 44 2.0 5 20 50 2.1 5.6 21 56 V V mA mA 58 Final Version: DM9102D-DS-F01 May 10, 2006 8.4 AC Electrical Characteristics & Timing Waveforms 8.4.1 PCI Clock Specifications Timing tHIGH 2.0V tLOW 0.8V tR tF tCYCLE Symbol tR tF tCYCLE tHIGH tLOW Parameter PCI_CLK Rising Time PCI_CLK Falling Time Cycle Time PCI_CLK High Time PCI_CLK Low Time Min. 25 12 12 Typ. 30 - Max. 4 4 - Unit ns ns ns ns ns Conditions - 8.4.2 Other PCI Signals Timing Diagram 2.5V cLK tVAL(max) tVAL(min) Output tOFF tON Input tH tSU Symbol tVAL tON tOFF tSU tH Parameter Clk-To-Signal Valid Delay Float-To-Active Delay From Clk Active-To-Float Delay From Clk Input Signal Valid Setup Time Before Clk Input Signal Hold Time From Clk Min. 2 2 7 0 Typ. - Max. 13 28 - Unit ns ns ns ns ns Conditions Cload = 50 pF - Final Version: DM9102D-DS-F01 May 10, 2006 59 8.4.3 Boot ROM Timing tC B A D t1 A D L t2 A D L t3 A D L t4 A D L RO M CS M D [7:0] A D [31:0] C B E L [3:0] F ram e# tR C Irdy # T rdy # D e vs el# tA D T D Symbol tRC tCBAD T1ADL T2ADL T3ADL T4ADL tADTD Parameter Read Cycle Time Bus Command to First Address Delay First Address Length Second Address Length Third Address Length Fourth Address Length End of Address to Trdy Active Min. - Typ. 50 18 8 8 8 7 1 Max. - Unit PCI clock PCI clock PCI clock PCI clock PCI clock PCI clock PCI clock Conditions - 8.4.4 EEPROM Read Timing tECSC tCSKD ROMCS EECK EEDO tECKC tEDSP Symbol tECKC tECSC tCSKD tEDSP Parameter Serial ROM Clock EECK Period Read Cycle Time Delay from ROMCS High to EECK High Setup Time of EEDO to EECK Min. - Typ. 2560 71680 1600 960 Max. - Unit ns ns ns ns Conditions - 60 Final Version: DM9102D-DS-F01 May 10, 2006 8.4.5 TP Interface Symbol tTR/F tTM tTDC tT/T XOST Parameter 100TX+/- Differential Rise/Fall Time 100TX+/- Differential Rise/Fall Time Mismatch 100TX+/- Differential Output Duty Cycle Distortion 100TX+/- Differential Output Peak-to-Peak Jitter 100TX+/- Differential Voltage Overshoot Min. 3.0 0 0 0 0 Typ. Max. 5.0 0.5 0.5 1.4 5 Unit ns ns ns ns % Conditions 8.4.6 Oscillator/Crystal Timing Symbol tCKC TPWH TPWL Parameter OSC Cycle Time OSC Pulse Width High OSC Pulse Width Low Min. 39.998 16 16 Typ. 40 20 20 Max. 40.002 24 24 Unit ns ns ns Conditions +/-50ppm 8.4.7 Auto-negotiation and Fast Link Pulse Timing Parameters Symbol t1 t2 t3 t4 t5 Parameter Clock/Data Pulse Width Clock Pulse To Data Pulse Period Clock Pulse To Clock Pulse Period FLP Burst Width FLP Burst To FLP Burst Period Clock/Data Pulses in a Burst Min. 55.5 111 8 17 Typ. 100 62.5 125 2 16 Max. 69.5 139 24 33 Unit ns us us ms ms # Conditions DATA = 1 8.4.8 Fast Link Pulses Clock Pulse Data Pulse Clock Pulse FAST LINK PULSES t1 t2 t3 FLP Burst t1 FLP Burst FLP Bursts t4 t5 Final Version: DM9102D-DS-F01 May 10, 2006 61 9. Application Notes 9.1 Network Interface Signal Routing Place the transformer as close as possible to the RJ-45 connector. Place all the 50 resistors as close as possible to the DM9102D RX and TX pins. Traces routed from RX and TX to the transformer should run in close pairs directly to the transformer. The designer should be careful not to cross the transmit and receive pairs. As always, vias should be avoided as much as possible. The network interface should be void of any signals other than the TX and RX pairs between the RJ-45 to the transformer and the transformer to the DM9102D. There should be no power or ground planes in the area under the network side of the transformer to include the area under the RJ-45 connector (Refer to Figure 9-4-1 and 9-5). Keep chassis ground away from all active signals. The RJ-45 connector and any unused pins should be tied to chassis ground through a resistor divider network and a 2KV bypass capacitor. The Band Gap resistor should be placed as physically close to pin 101 and 102 as possible (refer to Figure 9-1 and 9-2 ). The designer should not run any high-speed signal near the Band Gap resistor placement. 9.2 10Base-T/100Base-TX Application Figure 9-1 62 Final Version: DM9102D-DS-F01 May 10, 2006 9.3 10Base-T/100Base-TX (Power Reduction and non-auto-MDIX Application) Figure 9-2 Final Version: DM9102D-DS-F01 May 10, 2006 63 9.4 Power Supply Decoupling Capacitors * Place all the decoupling capacitors for all the power supply pins as close as possible to the power pads of the DM9102D (no more than 2.5mm from the pins mentioned above.) The recommended decoupling capacitor is 0.1 F or 0.01 F. The decoupling of PCB layout and power supply should provide sufficient decoupling to achieve the following when measured at the device: (1) All DVDDs and AVDDs should be within 50m Vpp of each other, (2) All DGNDs and AGNDs should be within 50m Vpp of each other. (3) The resultant AC noise voltage measured across each DVDD/DGND set and AVDD/AGND set should be less than 100m Vpp. The 0.1-0.01 F decoupling capacitor should be connected between each DVDD/DGND set and AVDD/AGND set be placed as close as possible to the pins of DM9102D. The conservative approach is to use two decoupling capacitors on each DVDD/DGND set and AVDD/AGND set. The 0.1F capacitor is used for low frequency noise and the 0.01F one is for high frequency noise on the power supply. The AVDD connection to the transmit center tap of the magnetic has to be well decoupled to minimize common mode noise injection from the power supply into the twisted pair cable. It is recommended that a 0.01 F decoupling capacitor should be placed between the center tap AVDD to AGND ground plane. This decoupling capacitor should be placed as close as possible to the center tap of the magnetic. * * * Figure 9-3 64 Final Version: DM9102D-DS-F01 May 10, 2006 9.5 Ground Plane Layout * Place a single ground plane approach to minimize EMI. Bad ground plane partitioning can cause more EMI emissions that could make the network interface card (NIC) not compliant with specific FCC part 15 and CE regulations. The ground plane must be separated into Analog ground domain and Digital ground domain. The line which connects the analog ground domain and digital ground domain should be far away from the AGND pins of DM9102D (see Figure 9-4-1). All AGND pins (pin 100, 107, 108) could not directly short each other (see Figure 9-4-3). It must be directly connected to the analog ground domain (see Figure 9-4-2). The analog ground domain area is as large as possible * * * 25MHz X'tal Figure 9-4-1 Analog ground domain Analog ground domain AGND AGND AGND AGND AGND AGND Better Worse! AGND direct short Digital ground domain Digital ground domain Figure 9-4-2 Figure 9-4-3 Final Version: DM9102D-DS-F01 May 10, 2006 65 9.6 Power Plane Partitioning * The power planes are approximately illustrated in Figure 9-4. The ferrite bead used should have an impedance 100 at 100MHz and 250mA above. A suitable bead is the Panasonic surface mound bead, part number EXCCL4532U or an equivalent. 10 F, 0.1 F and 0.01 F electrolytic bypass capacitors should be connected between VDD and GND at each side of the ferrite bead. Separate analog power planes from noisy logic power planes. * Figure 9-5 66 Final Version: DM9102D-DS-F01 May 10, 2006 9.7 Magnetics Selection Guide * and qualify all magnetic specifications before Refer to the following tables 9-1 and 9-2 for using them in an application. The magnetics 10/100M magnetic sources and specification listed in the following tables are electrical requirements. The magnetics which meets these equivalents, but may not be pin-to-pin equivalents. requirements are available from a variety of magnetic manufacturers. Designers should test Manufacturer Part Number PE-68515, H1078, H1012, H1102 Pulse Engineering LF8200, LF8221x Delta 20PMT04, 20PMT05, PH163112 , YCL 0303 YCL PH163539 *(Auto-MDIX) TG22-3506ND, TD22-3506G1, TG22-S010ND, TG22-S012ND Halo TG110-S050N2 NPI 6181-37, NPI 6120-30, NPI 6120-37 Nano Pulse Inc. NPI 6170-30 PT41715 Fil-Mag S558-5999-01, S558-5999-W2 Bel Fuse ST6114, ST6118 Valor HS2123, HS2213 Macronics TS6121C,16ST8515,16ST1086 Bothhand * Table 9-1: 10/100M Magnetic Sources Parameter Tx / RX turns ratio Inductance Insertion loss Return loss Values 1:1 CT / 1:1 350 1.1 -18 -14 -12 Differential to common mode rejection Transformer isolation -40 -30 1500 Units H ( Min ) dB ( Max ) dB ( Min ) dB ( Min ) dB ( Min ) dB ( Min ) dB ( Min ) V Test Condition 1 - 100 MHz 1 -30 MHz 30 - 60 MHz 60 - 80 MHz 1 - 60 MHz 60 - 100 MHz - Table 9-2: Magnetic Specification Requirements Final Version: DM9102D-DS-F01 May 10, 2006 67 9.8 Crystal Selection Guide * A crystal can be used to generate the 25MHz reference clock instead of an oscillator. The crystal must be a fundamental type, PARAMETER series-resonant, connected to X1 and X2, and shunt to ground with 22pF capacitors. (See Table 9-3 and Figure 9-66.) SPEC Type Frequency Equivalent Series Resistance Load Capacitance Case Capacitance Power Dissipation Fundamental, series-resonant 25 MHz +/-0.005% 25 ohms max 22 pF typ. 7 pF max. 1mW max. Table 9-3: Crystal Specifications X2 97 98 X1 25MHz 22pf AGND AGND 22pf Figure 9-6 Crystal Circuit Diagram 68 Final Version: DM9102D-DS-F01 May 10, 2006 10. Package Information LQFP 128L Outline Dimensions Unit: Inches/mm y Symbol A A1 A2 b c D E e F GD HD HE L L1 y Dimensions In Inches 0.063 Max. 0.004 0.002 0.055 0.002 0.006 +0.003 -0.001 D Dimensions In mm 1.60 Max. 0.1 0.05 1.4 0.05 0.16 +0.07 -0.03 0.006 0.002 0.551 0.005 0.551 0.005 0.016 BSC. 0.494 NOM. 0.606 NOM. 0.630 0.006 0.630 0.006 0.024 0.006 0.039 Ref. 0.003 Max. 0 ~ 12 0.15 0.05 14.00 0.13 14.00 0.13 0.40 BSC. 12.56 NOM. 15.40 NOM. 16.00 0.15 16.00 0.15 0.60 0.15 1.00 Ref. 0.08 Max. 0 ~ 12 Notes: 1. Dimension D & E do not include resin fins. 2. Dimension GD is for PC Board surface mount, pad pitch design reference only. 3. All dimensions are based on metric system. Final Version: DM9102D-DS-F01 May 10, 2006 69 11. Ordering Information Part Number DM9102DE DM9102DEP Pin Count 128 128 Package LQFP LQFP(Pb-Free) reference purposes only. DAVICOM`s terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer's orders shall be based on these terms. Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification, and the provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description, regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for Company Overview DAVICOM Semiconductor, Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that are the industry's best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: No.6 Li-Hsin Rd. VI, Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797 FAX: 886-3-6669831 WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function. 70 Final Version: DM9102D-DS-F01 May 10, 2006 |
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